Diode array and method of making thereof

• US 7,846,782 B2
• Filed: 09/28/2007
• Issued: 12/07/2010
• Est. Priority Date: 09/28/2007
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Clark, Mark H., Konevecki, Michael, Maxwell, Steven, Raghuram, Usha
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): PATHAK, SHANTANU
• Application Number:
  US11/864,532
• Publication Number:
  US 20090085153A1
• Time in Patent Office: 1,166 Days
• Field of Search: None
• US Class Current: 438/131
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.

Claims

1. A method of making a non-volatile memory device, comprising:

providing a substrate having a substrate surface; and

forming a non-volatile memory array over the substrate surface;

wherein;

the non-volatile memory array comprises an array of semiconductor diodes;

each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface;

each semiconductor diode is disposed horizontally with respect to the substrate surface;

in each semiconductor diode, a p-type semiconductor region and an n-type semiconductor region are equidistant from the substrate surface;

the step of forming the non-volatile memory array comprises monolithically forming a plurality of device levels of the semiconductor diodes such that the plurality of device levels are stacked in a vertical direction with respect to the substrate surface; and

the step of forming the non-volatile memory array further comprises;

forming a first semiconductor layer over the substrate surface;

forming a first insulating layer over the first semiconductor layer;

forming a first trench extending through the first semiconductor layer and the first insulating layer;

doping first sidewalls of the first semiconductor layer exposed in the first trench with dopants of the first conductivity type to form first conductivity type regions in the first semiconductor layer;

forming a first conductive layer in the first trench and over the first insulating layer;

planarizing the first conductive layer such that the first conductive layer forms a first horizontal conductor in the first trench and the first horizontal conductor electrically contacts the first conductivity type regions in the first semiconductor layer;

forming an interlevel insulating layer over the first horizontal conductor;

forming a second semiconductor layer over the interlevel insulating layer;

forming a second insulating layer over the second semiconductor layer;

forming a second trench extending through the second semiconductor layer and the second insulating layer up to the interlevel insulating layer;

doping first sidewalls of the second semiconductor layer exposed in the second trench with dopants of the first conductivity type to form first conductivity type regions in the second semiconductor layer;

forming a second conductive layer in the second trench and over the second insulating layer;

planarizing the second conductive layer such that the second conductive layer forms a second horizontal conductor in the second trench and the second horizontal conductor electrically contacts the first conductivity type regions in the second semiconductor layer;

patterning the first semiconductor layer, the first insulating layer, the second semiconductor layer and the second insulating layer to expose second sidewalls of the first and the second semiconductor layers;

doping at least one exposed second sidewall of each of the first and the second semiconductor layers with dopants of a second conductivity type to form second conductivity type regions in the first and the second semiconductor layers; and

forming at least one vertical pillar conductor which electrically contacts the second conductivity type regions in the first and the second semiconductor layers.

2. The method of claim 1, wherein:

the step of forming the at least one vertical pillar conductor comprises forming at least two vertical pillar conductors such that a first vertical pillar conductor is separated from the first and the second horizontal conductors and from the second vertical pillar conductor along a first direction;

a first semiconductor diode is located in a first device level between the first vertical pillar conductor and the first horizontal conductor;

a second semiconductor diode is located in the first device level between the second vertical pillar conductor and the first horizontal conductor;

a third semiconductor diode is located in a second device level between the first vertical pillar conductor and the second horizontal conductor; and

a fourth semiconductor diode is located in the second device level between the second vertical pillar conductor and the second horizontal conductor.

3. The method of claim 2, further comprising:

patterning the first and the second semiconductor layers and the first and the second insulating layers to form isolation trenches between adjacent semiconductor diodes separated from each other along a second direction perpendicular to the first direction; and

filling the isolation trenches with an insulating material.

4. The method of claim 1, further comprising:

forming first silicide regions located between the first conductivity type regions in the first and the second semiconductor layers and the respective first and second horizontal conductors; and

forming second silicide regions located between the second conductivity type regions in the first and the second semiconductor layers and the at least one vertical pillar conductor.

5. The method of claim 1, further comprising:

patterning the second horizontal conductor such that a portion of the first horizontal conductor is exposed below the second horizontal conductor in a stepped configuration;

forming a first electrical connector in contact with the exposed portion of the first horizontal conductor; and

forming a second electrical connector in contact with the second horizontal conductor.

6. The method of claim 1, wherein the steps of doping the first and the second sidewalls of the first and the second semiconductor layers comprises halo doping the first and the second sidewalls.

7. A method of making a semiconductor device, comprising:

forming a first semiconductor layer over a substrate surface;

forming a first insulating layer over the first semiconductor layer;

forming a first trench extending through the first semiconductor layer and the first insulating layer;

doping first sidewalls of the first semiconductor layer exposed in the first trench with dopants of the first conductivity type to form first conductivity type regions in the first semiconductor layer;

forming a first conductive layer in the first trench and over the first insulating layer

planarizing the first conductive layer such that the first conductive layer forms a first horizontal conductor in the first trench and the first horizontal conductor electrically contacts the first conductivity type regions in the first semiconductor layer;

forming an interlevel insulating layer over the first horizontal conductor;

forming a second semiconductor layer over the interlevel insulating layer;

forming a second insulating layer over the second semiconductor layer;

forming a second trench extending through the second semiconductor layer and the second insulating layer up to the interlevel insulating layer;

doping first sidewalls of the second semiconductor layer exposed in the second trench with dopants of the first conductivity type to form first conductivity type regions in the second semiconductor layer;

forming a second conductive layer in the second trench and over the second insulating layer;

planarizing the second conductive layer such that the second conductive layer forms a second horizontal conductor in the second trench and the second horizontal conductor electrically contacts the first conductivity type regions in the second semiconductor layer;

patterning the first semiconductor layer, the first insulating layer, the second semiconductor layer and the second insulating layer to expose second sidewalls of the first and the second semiconductor layers;

doping at least one exposed second sidewall of each of the first and the second semiconductor layers with dopants of a second conductivity type to form second conductivity type regions in the first and the second semiconductor layers; and

forming at least one vertical pillar conductor which electrically contacts the second conductivity type regions in the first and the second semiconductor layers.

8. The method of claim 7, wherein:

the step of forming the at least one vertical pillar conductor comprises forming at least two vertical pillar conductors such that a first vertical pillar conductor is separated from the first and the second horizontal conductors and from the second vertical pillar conductor along a first direction;

a first semiconductor diode is located in a first device level between the first vertical pillar conductor and the first horizontal conductor;

a second semiconductor diode is located in the first device level between the second vertical pillar conductor and the first horizontal conductor;

a third semiconductor diode is located in a second device level between the first vertical pillar conductor and the second horizontal conductor; and

a fourth semiconductor diode is located in the second device level between the second vertical pillar conductor and the second horizontal conductor.

9. The method of claim 8, further comprising:

patterning the first and the second semiconductor layers and the first and the second insulating layers to form isolation trenches between adjacent semiconductor diodes separated from each other along a second direction perpendicular to the first direction; and

filling the isolation trenches with an insulating material.

10. The method of claim 7, further comprising:

forming first silicide regions located between the first conductivity type regions in the first and the second semiconductor layers and the respective first and second horizontal conductors; and

forming second silicide regions located between the second conductivity type regions in the first and the second semiconductor layers and the at least one vertical pillar conductor.

11. The method of claim 7, further comprising:

patterning the second horizontal conductor such that a portion of the first horizontal conductor is exposed below the second horizontal conductor in a stepped configuration;

forming a first electrical connector in contact with the exposed portion of the first horizontal conductor; and

forming a second electrical connector in contact with the second horizontal conductor.

12. The method of claim 7, wherein the steps of doping the first and the second sidewalls of the first and the second semiconductor layers comprises halo doping the first and the second sidewalls.