Diode array and method of making thereof
First Claim
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1. A method of making a non-volatile memory device, comprising:
- providing a substrate having a substrate surface; and
forming a non-volatile memory array over the substrate surface;
wherein;
the non-volatile memory array comprises an array of semiconductor diodes;
each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface;
each semiconductor diode is disposed horizontally with respect to the substrate surface;
in each semiconductor diode, a p-type semiconductor region and an n-type semiconductor region are equidistant from the substrate surface;
the step of forming the non-volatile memory array comprises monolithically forming a plurality of device levels of the semiconductor diodes such that the plurality of device levels are stacked in a vertical direction with respect to the substrate surface; and
the step of forming the non-volatile memory array further comprises;
forming a first semiconductor layer over the substrate surface;
forming a first insulating layer over the first semiconductor layer;
forming a first trench extending through the first semiconductor layer and the first insulating layer;
doping first sidewalls of the first semiconductor layer exposed in the first trench with dopants of the first conductivity type to form first conductivity type regions in the first semiconductor layer;
forming a first conductive layer in the first trench and over the first insulating layer;
planarizing the first conductive layer such that the first conductive layer forms a first horizontal conductor in the first trench and the first horizontal conductor electrically contacts the first conductivity type regions in the first semiconductor layer;
forming an interlevel insulating layer over the first horizontal conductor;
forming a second semiconductor layer over the interlevel insulating layer;
forming a second insulating layer over the second semiconductor layer;
forming a second trench extending through the second semiconductor layer and the second insulating layer up to the interlevel insulating layer;
doping first sidewalls of the second semiconductor layer exposed in the second trench with dopants of the first conductivity type to form first conductivity type regions in the second semiconductor layer;
forming a second conductive layer in the second trench and over the second insulating layer;
planarizing the second conductive layer such that the second conductive layer forms a second horizontal conductor in the second trench and the second horizontal conductor electrically contacts the first conductivity type regions in the second semiconductor layer;
patterning the first semiconductor layer, the first insulating layer, the second semiconductor layer and the second insulating layer to expose second sidewalls of the first and the second semiconductor layers;
doping at least one exposed second sidewall of each of the first and the second semiconductor layers with dopants of a second conductivity type to form second conductivity type regions in the first and the second semiconductor layers; and
forming at least one vertical pillar conductor which electrically contacts the second conductivity type regions in the first and the second semiconductor layers.
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Abstract
A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface.
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Citations
12 Claims
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1. A method of making a non-volatile memory device, comprising:
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providing a substrate having a substrate surface; and forming a non-volatile memory array over the substrate surface; wherein; the non-volatile memory array comprises an array of semiconductor diodes; each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface; each semiconductor diode is disposed horizontally with respect to the substrate surface; in each semiconductor diode, a p-type semiconductor region and an n-type semiconductor region are equidistant from the substrate surface; the step of forming the non-volatile memory array comprises monolithically forming a plurality of device levels of the semiconductor diodes such that the plurality of device levels are stacked in a vertical direction with respect to the substrate surface; and the step of forming the non-volatile memory array further comprises; forming a first semiconductor layer over the substrate surface; forming a first insulating layer over the first semiconductor layer; forming a first trench extending through the first semiconductor layer and the first insulating layer; doping first sidewalls of the first semiconductor layer exposed in the first trench with dopants of the first conductivity type to form first conductivity type regions in the first semiconductor layer; forming a first conductive layer in the first trench and over the first insulating layer; planarizing the first conductive layer such that the first conductive layer forms a first horizontal conductor in the first trench and the first horizontal conductor electrically contacts the first conductivity type regions in the first semiconductor layer; forming an interlevel insulating layer over the first horizontal conductor; forming a second semiconductor layer over the interlevel insulating layer; forming a second insulating layer over the second semiconductor layer; forming a second trench extending through the second semiconductor layer and the second insulating layer up to the interlevel insulating layer; doping first sidewalls of the second semiconductor layer exposed in the second trench with dopants of the first conductivity type to form first conductivity type regions in the second semiconductor layer; forming a second conductive layer in the second trench and over the second insulating layer; planarizing the second conductive layer such that the second conductive layer forms a second horizontal conductor in the second trench and the second horizontal conductor electrically contacts the first conductivity type regions in the second semiconductor layer; patterning the first semiconductor layer, the first insulating layer, the second semiconductor layer and the second insulating layer to expose second sidewalls of the first and the second semiconductor layers; doping at least one exposed second sidewall of each of the first and the second semiconductor layers with dopants of a second conductivity type to form second conductivity type regions in the first and the second semiconductor layers; and forming at least one vertical pillar conductor which electrically contacts the second conductivity type regions in the first and the second semiconductor layers. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of making a semiconductor device, comprising:
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forming a first semiconductor layer over a substrate surface; forming a first insulating layer over the first semiconductor layer; forming a first trench extending through the first semiconductor layer and the first insulating layer; doping first sidewalls of the first semiconductor layer exposed in the first trench with dopants of the first conductivity type to form first conductivity type regions in the first semiconductor layer; forming a first conductive layer in the first trench and over the first insulating layer planarizing the first conductive layer such that the first conductive layer forms a first horizontal conductor in the first trench and the first horizontal conductor electrically contacts the first conductivity type regions in the first semiconductor layer; forming an interlevel insulating layer over the first horizontal conductor; forming a second semiconductor layer over the interlevel insulating layer; forming a second insulating layer over the second semiconductor layer; forming a second trench extending through the second semiconductor layer and the second insulating layer up to the interlevel insulating layer; doping first sidewalls of the second semiconductor layer exposed in the second trench with dopants of the first conductivity type to form first conductivity type regions in the second semiconductor layer; forming a second conductive layer in the second trench and over the second insulating layer; planarizing the second conductive layer such that the second conductive layer forms a second horizontal conductor in the second trench and the second horizontal conductor electrically contacts the first conductivity type regions in the second semiconductor layer; patterning the first semiconductor layer, the first insulating layer, the second semiconductor layer and the second insulating layer to expose second sidewalls of the first and the second semiconductor layers; doping at least one exposed second sidewall of each of the first and the second semiconductor layers with dopants of a second conductivity type to form second conductivity type regions in the first and the second semiconductor layers; and forming at least one vertical pillar conductor which electrically contacts the second conductivity type regions in the first and the second semiconductor layers. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification