Semiconductor layer structure and method of making the same

• US 7,846,814 B2
• Filed: 06/30/2008
• Issued: 12/07/2010
• Est. Priority Date: 06/21/2004
• Status: Expired due to Fees

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Primary Examiner(s): Tran; Long K
• Application Number:
  US12/165,475
• Publication Number:
  US 20080261380A1
• Time in Patent Office: 890 Days
• Field of Search: 438/138, 438/152, 438/455, 438/458, 438/488, 257/E21.088, 257/E21.122, 257/E21.214, 257/E21.388, 257/E21.123, 257/E21.572
• US Class Current: 438/455
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y10S 257/928 : with shorted PN or schottky junction other than emitter junction

Abstract

A method of forming a semiconductor structure includes providing a substrate and providing a detach region which is carried by the substrate. A device structure which includes a stack of crystalline semiconductor layers is provided, wherein the detach region is positioned between the device structure and substrate. The stack is processed to form a vertically oriented semiconductor device.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

providing a detach region which is carried by the substrate; and

providing a device structure which includes a stack of crystalline semiconductor layers;

wherein the detach region is positioned between the device structure and substrate.

2. The method of claim 1, wherein the stack of crystalline semiconductor layers includes a first layer with a first conductivity type positioned between second and third layers with opposite conductivity types.

3. The method of claim 2, wherein the first layer has a graded doping concentration.

4. The method of claim 1, wherein the device structure is formed by ion implantation.

5. The method of claim 1, wherein the detach region is formed after forming the device structure.

6. The method of claim 1, wherein the device structure consists of the stack of crystalline semiconductor layers.

7. The method of claim 1, wherein the device structure consists essentially of the stack of crystalline semiconductor layers.

8. A method of forming a semiconductor structure, comprising:

providing a substrate which consists essentially of single crystalline semiconductor material;

providing a detach region which is carried by the substrate; and

providing a device structure which consists essentially of a stack of crystalline semiconductor layers;

wherein the detach region is positioned between the device structure and substrate.

9. The method of claim 8, wherein the stack of doped semiconductor layers includes a p+np+ junction.

10. The method of claim 8, wherein the stack of doped semiconductor layers includes a n+pn+ junction.

11. The method of claim 8, wherein a portion of the device structure has a graded doping concentration.

12. The method of claim 8, wherein the detach region is formed before the device structure.

13. The method of claim 8, further including forming a mesa structure from the device structure.

14. The method of claim 8, wherein the detach region does not include semiconductor material.

15. A method of forming a semiconductor structure, comprising:

providing a first semiconductor substrate;

providing a detach region which is carried by the first semiconductor substrate, and

providing a stack of crystalline semiconductor layers which is carried by the first semiconductor substrate, the detach region being positioned between the first semiconductor substrate and the stack.

16. The method of claim 15, further including coupling a second semiconductor substrate to the stack of crystalline semiconductor layers using bonding.

17. The method of claim 16, further including detaching the first semiconductor substrate using the detach region.

18. The method of claim 17, further including forming a mesa structure with the stack of crystalline semiconductor layers, the mesa structure being formed after the second semiconductor substrate is bonded to the stack of crystalline semiconductor layers.

19. The method of claim 18, further including forming a vertically oriented semiconductor device with the mesa structure.

20. The method of claim 15, wherein the stack consists essentially of semiconductor material.