Eutectic flow containment in a semiconductor fabrication process

• US 7,846,815 B2
• Filed: 03/30/2009
• Issued: 12/07/2010
• Est. Priority Date: 03/30/2009
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Karlin, Lisa H., Desai, Hemant D.
• Primary Examiner(s): Smith, Matthew S
• Assistant Examiner(s): FAN, SU JYA
• Application Number:
  US12/414,324
• Publication Number:
  US 20100244159A1
• Time in Patent Office: 617 Days
• Field of Search: 438/455, 438/456, 438/106, 438/107, 438/119, 257/734, 257/678, 257/684, 257/E23.001
• US Class Current: 438/456
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure.

Claims

1. A semiconductor fabrication process, comprising:

forming a first bonding structure on a first surface of a cap wafer;

forming a device cavity in the first surface of the cap wafer;

forming a second bonding structure on a first surface of a device wafer;

forming a device structure on the device wafer;

forming a eutectic flow containment structure on at least one of the cap wafer and the device wafer, the eutectic flow containment structure comprising an exterior flow containment micro-levee (FCML), the exterior FCML comprising an elongated ridge overlying the first surface of the device wafer and extending substantially parallel to the second bonding structure, wherein a perimeter of the exterior FCML encloses a perimeter of the second bonding structure; and

bringing the first and second bonding structures into contact while maintaining at least one of the cap wafer and the device wafer at a predetermined temperature to create a eutectic bond from the first and second bonding structures.

2. The process of claim 1, further comprising forming an interior FCML wherein a perimeter of the FCML lies within a perimeter of the second bonding structure.

3. The process of claim 1, wherein the exterior FCML comprises an annular structure circumventing the device structure and wherein the FCML includes a silicon portion.

4. The process of claim 3, wherein the silicon portion of the exterior FCML comprises polycrystalline silicon and wherein the exterior FCML further includes a metal portion overlying the silicon portion.

5. The process of claim 1, wherein forming the at least one flow containment structure further comprises forming at least one flow containment micro-cavity on the cap wafer.

6. The process of claim 1, wherein one of the first and second bonding structures comprises a first eutectic element and another of the first and second bonding structures comprises a second eutectic element, wherein the first eutectic element and the second eutectic element form the eutectic bond.

7. A semiconductor fabrication process, comprising:

forming a first bonding structure on a first surface of a cap wafer;

forming a device cavity in the first surface of the cap wafer;

forming a second bonding structure on a first surface of a device wafer;

forming a device structure on the device wafer;

forming a plurality of eutectic flow containment structures on at least one of the cap wafer and the device wafer, each eutectic flow containment structure being selected from a flow containment micro-cavity (FCMC) and a flow containment micro-levee (FCML); and

bringing the first and second bonding structures into contact while maintaining at least one of the cap wafer and the device wafer at a predetermined temperature to create a eutectic bond from the first and second bonding structures;

wherein forming the plurality of flow containment structures comprises forming an exterior flow containment micro-cavity (FCMC) on the cap wafer wherein a perimeter of the exterior FCMC encloses a perimeter of the first bonding structure.

8. The process of claim 7, further comprising forming an interior FCMC wherein a perimeter of the interior FCMC lies within a perimeter of the first bonding structure.

9. The process of claim 7, wherein forming the exterior FCMC comprises forming an annular void circumventing the device cavity.

10. A semiconductor fabrication process, comprising:

forming a first bonding structure on a first surface of a cap wafer;

forming a device cavity in the first surface of the cap wafer;

forming a second bonding structure on a first surface of a device wafer;

forming a device structure on the device wafer;

forming a eutectic flow containment structure on at least one of the cap wafer and the device wafer, the eutectic flow containment structure comprising an exterior flow containment structure, the exterior flow containment structure comprising an elongated ridge overlying the first surface of the device wafer and extending substantially parallel to the second bonding structure, wherein a perimeter of the exterior flow containment structure encloses a perimeter of the second bonding structure; and

creating a eutectic bond between the first and second bonding structures.

11. The process of claim 10, wherein the exterior flow containment structure comprises an exterior flow containment micro-levee.