Dense chevron non-planar field effect transistors and method
First Claim
1. An integrated circuit structure comprising:
- a substrate;
a limited area within said substrate, said limited area being essentially rectangular in shape;
multiple parallel angled semiconductor fins on said substrate diagonally traversing in said limited area, each of said fins comprising a discrete linear structure; and
multiple parallel gates on said substrate extending laterally across a width of said limited area and traversing said fins,wherein said gates have a pre-selected first pitch,wherein at least one of said fins is traversed by more than one of said gates,wherein said fins are positioned diagonally relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern with none of said fins being only partially traversed by a gate and none of said gates traversing an end of a fin, andwherein said fins further have a second pitch that is predetermined, based on said angle and said first pitch, in order to achieve said periodic pattern.
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Abstract
Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.
19 Citations
19 Claims
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1. An integrated circuit structure comprising:
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a substrate; a limited area within said substrate, said limited area being essentially rectangular in shape; multiple parallel angled semiconductor fins on said substrate diagonally traversing in said limited area, each of said fins comprising a discrete linear structure; and multiple parallel gates on said substrate extending laterally across a width of said limited area and traversing said fins, wherein said gates have a pre-selected first pitch, wherein at least one of said fins is traversed by more than one of said gates, wherein said fins are positioned diagonally relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern with none of said fins being only partially traversed by a gate and none of said gates traversing an end of a fin, and wherein said fins further have a second pitch that is predetermined, based on said angle and said first pitch, in order to achieve said periodic pattern. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit structure comprising:
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a substrate; a limited area within said substrate, said limited area being essentially rectangular in shape; multiple parallel angled semiconductor fins on said substrate in said limited area, each of said fins comprising a discrete linear structure; and multiple parallel gates on said substrate extending laterally across a width of said limited area and traversing said fins, wherein said gates have a pre-selected first pitch, wherein at least one of said fins is traversed by more than one of said gates, wherein said fins are positioned diagonally relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern with none of said fins being only partially traversed by a gate and none of said gates traversing an end of a fin, wherein said pre-selected periodic pattern repeats within said limited area at every Nth gate and at every Mth fin, wherein N and M are pre-selected whole numbers greater than zero and at least one of N and M is greater than 1, and wherein said fins further have a second pitch that is predetermined, based on said angle, a ratio of N over M, and said first pitch, in order to achieve said periodic pattern. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. An integrated circuit structure comprising:
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a substrate; a limited area within said substrate, said limited area being essentially rectangular in shape; multiple parallel angled semiconductor fins on said substrate in diagonally traversing said limited area, each of said fins comprising a discrete linear structure and at least some of said fins having different lengths; multiple parallel gates on said substrate extending laterally across a width of said limited area and traversing said fins, wherein said gates have a pre-selected first pitch, wherein at least one of said fins is traversed by more than one of said gates, wherein said fins are positioned diagonally relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern with none of said fins being only partially traversed by a gate and none of said gates traversing an end of a fin, wherein said pre-selected periodic pattern repeats within said limited area at every Nth gate and at every Mth fin, N and M being pre-selected whole numbers greater than zero, and wherein said fins further have a second pitch that is predetermined, based on said angle, a ratio of N over M, and said first pitch, in order to achieve said periodic pattern. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification