Semiconductor device and manufacturing method thereof

• US 7,847,321 B2
• Filed: 02/27/2006
• Issued: 12/07/2010
• Est. Priority Date: 02/28/2005
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Hara, Akito
• Primary Examiner(s): Smith; Bradley K
• Assistant Examiner(s): Tran; Tony
• Application Number:
  US11/362,530
• Publication Number:
  US 20060202234A1
• Time in Patent Office: 1,744 Days
• Field of Search: 257/213
• US Class Current: 257/213
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×10¹⁸ cm⁻³ to 5.0×10¹⁹ cm⁻³. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.

Claims

1. A semiconductor device, comprising:

a field effect transistor including a channel region formed in a semiconductor substrate, source and drain extension regions having a first depth and formed to both sides of the channel region in the semiconductor substrate, and source and drain regions having a second depth greater than the first depth and located at outer sides of the source and drain extension regions;

a strain generating layer including SiGe or SiC formed to apply a stress to the channel region of the field effect transistor; and

an impurity region located along an interface between the strain generating layer and the semiconductor substrate,

wherein the impurity region contains at least one of oxygen and nitrogen of concentration 1.0×

10¹⁸ cm<sup>−

3</sup> to 5.0×

10¹⁹ cm<sup>−

3</sup>.

2. The semiconductor device as claimed in claim 1, wherein the concentration peak of the oxygen or the nitrogen resides in the impurity region.

3. The semiconductor device as claimed in claim 1, wherein the strain generating layer is a global strain generating layer located under the channel region.

4. The semiconductor device as claimed in claim 1, wherein the strain generating layer is a localized strain generating layer located at outer sides of the source and drain regions.

5. The semiconductor device as claimed in claim 1, wherein the strain generating layer is located in the horizontal direction with respect to the channel region, and applies a uniaxial stress to the channel region.

6. The semiconductor device as claimed in claim 1, wherein the strain generating layer is located in the vertical direction with respect to the channel region, and applies a biaxial stress to the channel region.

7. The semiconductor device as claimed in claim 1, wherein a concentration peak is set along a boundary between the strain generating layer and the semiconductor substrate in which the channel region is provided.

8. A semiconductor device, comprising:

a field effect transistor including a channel region formed in a semiconductor substrate, and source and drain regions formed to both sides of the channel region in the semiconductor substrate;

a strain generating layer including SiGe or SiC formed to apply a stress to the channel region of the field effect transistor; and

a self-interstitial atoms/vacancies layer containing self-interstitial atoms and/or vacancies located along an interface between the strain generating layer and the semiconductor substrate,

wherein the self-interstitial atoms/vacancies layer contains self-interstitial atoms and/or vacancies of concentration 1.0×

10¹⁸ cm<sup>−

3</sup> to 5.0×

10¹⁹ cm<sup>−

3</sup>, and at least a portion of the self-interstitial atoms and/or vacancies exist as a cluster.

9. The semiconductor device as claimed in claim 8, wherein the strain generating layer is a global strain generating layer located under the channel region.

10. The semiconductor device as claimed in claim 8, wherein the strain generating layer is a localized strain generating layer located at outer sides of the source and drain regions.

11. The semiconductor device as claimed in claim 8, wherein the concentration peak of the self-interstitial atoms and/or vacancies resides in the interstitial atoms/vacancies layer.

12. The semiconductor device as claimed in claim 8, wherein the strain generating layer is located in the horizontal direction with respect to the channel region, and applies a uniaxial stress to the channel region.

13. The semiconductor device as claimed in claim 8, wherein the strain generating layer is located in the vertical direction with respect to the channel region, and applies a biaxial stress to the channel region.

14. The semiconductor device as claimed in claim 8, wherein a concentration peak is set along a boundary between the strain generating layer and the semiconductor substrate in which the channel region is provided.