Semiconductor memory having both volatile and non-volatile functionality and method of operating

• US 7,847,338 B2
• Filed: 10/23/2008
• Issued: 12/07/2010
• Est. Priority Date: 10/24/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Ngo; Ngan
• Application Number:
  US12/256,868
• Publication Number:
  US 20090108322A1
• Time in Patent Office: 775 Days
• Field of Search: 257/315, 257/316, 257/E29.129, 257/E29.3
• US Class Current: 257/316
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/225 Preventing erasure, programming or reading when power supply voltages are outside the required ranges
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 : Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/056 : the transistor being a FinFET
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 : the transistor being a FinFET
• CPC Class Codes: H10B 12/50 : Peripheral circuit region structures
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/42 : Simultaneous manufacture of periphery and memory cells
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer.

Claims

1. A semiconductor memory cell comprising:

a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory;

first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type;

first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region;

a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell;

a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and

a second insulating layer positioned between the floating gates or trapping layers and the control gate;

the substrate including an isolation layer that isolates the floating substrate region from the substrate below the isolation layer.

2. The memory cell of claim 1, wherein the isolation layer comprises a buried layer of the second conductivity type.

3. The semiconductor memory of cell of claim 1, wherein the substrate comprises a silicon-on-insulator (SOI) substrate.

4. The semiconductor memory cell of claim 1, wherein the isolation layer comprises a buried oxide insulating layer.

5. The semiconductor memory cell of claim 1, wherein the fin structure extends substantially perpendicularly from a plane of the substrate, forming a three-dimensional memory cell.

6. The semiconductor memory cell of claim 1, wherein the control gate is capacitively coupled to the floating gates or trapping layers and insulated from the floating gates or trapping layers by a dielectric layer.

7. The semiconductor memory cell of claim 1, wherein the first conductivity type is “

p”

type and the second conductivity type is “

n”

type.

8. The semiconductor cell of claim 1, wherein the floating substrate region is configured so that data can be written thereto by hot hole injection.

9. The semiconductor cell of claim 1, wherein when power to the cell is interrupted, data transfer from the floating substrate region to the floating gates or trapping layers occurs and the floating gates or trapping layers store the data as non-volatile memory.

10. The semiconductor cell of claim 1, wherein the floating gates or trapping layers store a charge in non-volatile memory that is complementary to a charge that was stored in the floating substrate region at a time when the power is interrupted.

11. The semiconductor cell of claim 9, wherein when power is restored to the cell, data transfer from the floating gates or trapping layers to the floating substrate region occurs and the cell functions as volatile memory.

12. The semiconductor memory cell of claim 11, wherein a state of the floating gates or trapping layers is set to a predetermined state after the data is transferred from the floating gates or trapping layers to the floating substrate region.

13. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a binary cell.

14. The semiconductor memory cell of claim 1, wherein the semiconductor memory cell functions as a multi-level cell.