Memory utilizing oxide-nitride nanolaminates

• US 7,847,344 B2
• Filed: 07/08/2002
• Issued: 12/07/2010
• Est. Priority Date: 07/08/2002
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US10/190,689
• Publication Number:
  US 20040004247A1
• Time in Patent Office: 3,074 Days
• Field of Search: 257314-317, 257319-322, 257/324, 257/E29.309, 257/302, 257328-331, 257/E21.21, 257/E27.103, 438/216, 438/261, 438/591, 438/593
• US Class Current: 257/330
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.

Claims

1. A transistor, comprising:

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator;

wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench, and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor;

wherein the gate insulator includes oxide-nitride nanolaminate layers formed using atomic layer deposition techniques;

wherein a nitride layer in the nanolaminate layers provides a positive conduction band offset with silicon; and

operation circuitry coupled to the transistor to program the transistor in a reverse direction and to read the transistor in a forward direction.

2. The transistor of claim 1, wherein the nitride layer provides an electron affinity higher than an oxide layer electron affinity.

3. The transistor of claim 1, wherein the nitride layer includes aluminum.

4. The transistor of claim 1, wherein the nitride layer includes gallium.

5. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

6. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

7. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

8. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

9. The transistor of claim 1, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

10. A vertical multistate cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers adapted to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor;

a transmission line coupled to the second source/drain region; and

wherein the MOSFET is a programmed MOSFET having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

11. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include silicon nitride.

12. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

13. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include gallium nitride.

14. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

15. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

16. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

17. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

18. The vertical multistate cell of claim 10, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

19. The vertical multistate cell of claim 10, wherein the first source/drain region of the MOSFET includes a source region and the second source/drain region of the MOSFET includes a drain region.

20. The vertical multistate cell of claim 19, wherein the second voltage threshold region (b 2) in the channel is adjacent the source region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the drain region.

21. The multistate cell of claim 20, wherein the Vt2 has a higher voltage threshold than the Vt1.

22. The vertical multistate cell of claim 10, wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

23. A vertical multistate cell, comprising:

a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate insulator wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

a wordline coupled to the gate;

wherein the source region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor;

a bit line coupled to the drain region; and

wherein the MOSFET is a programmed MOSFET having a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1.

24. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include silicon nitride.

25. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

26. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include gallium nitride.

27. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

28. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

29. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

30. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

31. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

32. The vertical multistate cell of claim 23, wherein the oxide-nitride nanolaminate layers have atomic dimensions with precisely controlled interfaces and layer thickness formed by atomic layer deposition (ALD).

33. The vertical multistate cell of claim 23, wherein the gate insulator has a thickness of approximately 1-10 nanometers (nm).

34. A transistor array, comprising:

a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers;

a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array;

a number of word lines coupled to the gate of each transistor cell along columns of the memory array;

wherein the first source/drain regions are integrally formed as common sourcelines that are shared between pairs of vertical transistors separated by a trench and wherein the pairs of vertical transistors are configured to compare a first transistor of each pair with a second transistor of each pair, the second transistor serving as a reference transistor; and

wherein at least one of transistor cells is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).

35. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include silicon nitride.

36. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

37. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include gallium nitride.

38. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

39. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

40. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

41. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

42. The transistor array of claim 34, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.

43. The transistor array of claim 34, wherein the one of a number of charge levels trapped in the gate insulator includes a charge adjacent to the source of approximately 100 electrons.

44. The transistor array of claim 34, wherein the first source/drain region of the transistor cell includes a source region and the second source/drain region of the transistor cell includes a drain region.

45. The transistor array of claim 34, wherein the second voltage threshold region (Vt2) in the channel is adjacent the first source/drain region, and wherein the first voltage threshold region (Vt1) in the channel is adjacent the second source/drain region, and wherein Vt2 has a higher voltage threshold than the Vt1.

46. The transistor array of claim 34, wherein the gate insulator of each transistor cell has a thickness of approximately 1-10 nanometers (nm).

47. The transistor array of claim 34, wherein the number of transistor cells extending from a substrate operate as equivalent to a transistor having a size equal to or than 1.0 lithographic feature squared (1F2).

48. A programmable logic array, comprising:

a plurality of input lines for receiving an input signal;

a plurality of output lines; and

one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including;

a first source/drain region;

a second source/drain region;

a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator;

wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; and

wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers and the transistor cell is a programmed transistor cell having charge trapped in the gate insulator adjacent to the first source/drain region or second source/drain region configured as a source region.

49. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include silicon nitride.

50. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include aluminum nitride.

51. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include gallium nitride.

52. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include gallium aluminum nitride.

53. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include tantalum aluminum nitride.

54. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include titanium silicon nitride.

55. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include titanium aluminum nitride.

56. The programmable logic array of claim 48, wherein the oxide-nitride nanolaminate layers include tungsten aluminum nitride.