Memory utilizing oxide-nitride nanolaminates
First Claim
Patent Images
1. A transistor, comprising:
- a first source/drain region;
a second source/drain region;
a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator;
wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench, and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor;
wherein the gate insulator includes oxide-nitride nanolaminate layers formed using atomic layer deposition techniques;
wherein a nitride layer in the nanolaminate layers provides a positive conduction band offset with silicon; and
operation circuitry coupled to the transistor to program the transistor in a reverse direction and to read the transistor in a forward direction.
8 Assignments
0 Petitions
Accused Products
Abstract
Structures, systems and methods for transistors utilizing oxide-nitride nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide-nitride nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers.
-
Citations
56 Claims
-
1. A transistor, comprising:
-
a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench, and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; wherein the gate insulator includes oxide-nitride nanolaminate layers formed using atomic layer deposition techniques; wherein a nitride layer in the nanolaminate layers provides a positive conduction band offset with silicon; and operation circuitry coupled to the transistor to program the transistor in a reverse direction and to read the transistor in a forward direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A vertical multistate cell, comprising:
-
a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, wherein the gate insulator includes oxide-nitride nanolaminate layers adapted to trap charge in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; a transmission line coupled to the second source/drain region; and wherein the MOSFET is a programmed MOSFET having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. A vertical multistate cell, comprising:
-
a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate, the MOSFET having a source region, a drain region, a channel region between the source region and the drain region, and a gate separated from the channel region by a gate insulator wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a wordline coupled to the gate; wherein the source region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; a bit line coupled to the drain region; and wherein the MOSFET is a programmed MOSFET having a number of charge levels trapped in the gate insulator adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) adjacent to the drain region and a second voltage threshold region (Vt2) adjacent to the source region, the Vt2 having a greater voltage threshold than Vt1. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
-
-
34. A transistor array, comprising:
-
a number of transistor cells formed on a substrate, wherein each transistor cell includes a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator, and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers; a number of bit lines coupled to the second source/drain region of each transistor cell along rows of the transistor array; a number of word lines coupled to the gate of each transistor cell along columns of the memory array; wherein the first source/drain regions are integrally formed as common sourcelines that are shared between pairs of vertical transistors separated by a trench and wherein the pairs of vertical transistors are configured to compare a first transistor of each pair with a second transistor of each pair, the second transistor serving as a reference transistor; and wherein at least one of transistor cells is a programmed transistor having one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2). - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
-
-
48. A programmable logic array, comprising:
-
a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a transistor cell including; a first source/drain region; a second source/drain region; a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator; wherein the first source/drain region is integrally formed as a common sourceline that is shared between a pair of vertical transistors separated by a trench and wherein the pair of vertical transistors are configured to compare a first transistor of the pair with a second transistor of the pair, the second transistor serving as a reference transistor; and wherein the gate insulator includes oxide-nitride nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the oxide-nitride nanolaminate layers and the transistor cell is a programmed transistor cell having charge trapped in the gate insulator adjacent to the first source/drain region or second source/drain region configured as a source region. - View Dependent Claims (49, 50, 51, 52, 53, 54, 55, 56)
-
Specification