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High performance strained CMOS devices

  • US 7,847,358 B2
  • Filed: 08/04/2006
  • Issued: 12/07/2010
  • Est. Priority Date: 10/16/2003
  • Status: Active Grant
First Claim
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1. A semiconductor structure formed on a substrate, comprising:

  • an n-FET device and a p-FET device;

    a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate; and

    the at least one overhang being selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow, wherein;

    for the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, andfor the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.

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