High performance strained CMOS devices

• US 7,847,358 B2
• Filed: 08/04/2006
• Issued: 12/07/2010
• Est. Priority Date: 10/16/2003
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B, Gluschenkov, Oleg G
• Primary Examiner(s): Garber; Charles D
• Assistant Examiner(s): Isaac; Stanetta D
• Application Number:
  US11/462,648
• Publication Number:
  US 20060270136A1
• Time in Patent Office: 1,586 Days
• Field of Search: 257/374, 257/E21.545
• US Class Current: 257/374
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate. The at least one overhang is selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow. For the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, and for the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.

Claims

1. A semiconductor structure formed on a substrate, comprising:

an n-FET device and a p-FET device;

a shallow trench isolation having at least one overhang is selectively configured to prevent oxidation induced stress in a determined portion of the substrate; and

the at least one overhang being selectively configured to prevent oxidation induced stress in at least one of a direction parallel to and a direction transverse to a direction of a current flow, wherein;

for the n-FET device, the at least one overhang is selectively arranged in directions of and transverse to a current flow, and

for the p-FET device, the at least one overhang is arranged transverse to the current flow to prevent performance degradation from compressive stresses.

2. The semiconductor structure of claim 1, wherein:

the determined portion of the substrate is an Si-SiO₂ interface adjacent to the shallow trench isolation; and

the at least one overhang extends beyond the Si-SiO₂ interface, preventing oxidation at or near the Si—

SiO₂ interface.

3. The semiconductor structure of claim 1, further comprising:

the n-FET device having a source and a drain with a direction of current flow for the n-FET device; and

the p-FET device having a source and drain with a direction of current flow for the p-FET device;

wherein the shallow trench isolation includes;

a first shallow trench isolation side for the n-FET device having at least one overhang configured to prevent oxidation induced stress in a direction parallel to the direction of current flow for the n-FET device; and

a second shallow trench isolation side for the n-FET device having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the n-FET device; and

a third shallow trench isolation side for the p-FET device having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the n-FET device.

4. The semiconductor structure of claim 3, wherein the shallow trench isolation further includes a fourth shallow trench isolation side for the p-FET device, the fourth shallow trench isolation being devoid of an overhang.

6. The semiconductor structure of claim 1, wherein the overhang includes a T-shaped structure.

7. The semiconductor structure of claim 6, wherein the determined portion of the substrate is an Si—

SiO₂ interface adjacent to the shallow trench isolation.

8. The semiconductor structure of claim 7, wherein the overhang includes a horizontal portion that extends beyond the Si—

SiO₂ interface by about 0.01 microns to 0.5 microns.

5. A semiconductor structure formed on a substrate, comprising:

an active device comprising an n-channel field effect transistor having a source, a drain, a gate, and a direction of current flow from the source to the drain; and

a first shallow trench isolation surrounding the n-channel field effect transistor, the first shallow trench isolation having;

a first shallow trench isolation side, the first shallow trench isolation side having at least one overhang configured to prevent oxidation induced stress in a direction parallel to the direction of current flow for the n-channel field effect transistor; and

a second shallow trench isolation side being transverse to the first shallow trench isolation side and having at least one overhang configured to prevent oxidation induced stress in a direction transverse to the direction of current flow for the n-channel field effect transistor.

9. A semiconductor structure formed on a substrate, comprising:

at least one p-FET device;

a shallow trench isolation surrounding the at least one p-FET device and comprising at least one overhang structured and arranged to prevent oxidation induced stress at least in a direction transverse to a direction of a current flow,

wherein the shallow trench isolation does not have an overhang in a direction parallel to the current flow.

10. A process for preventing oxidation induced stress in determined portions of a substrate, the process comprising:

at least one of;

forming a shallow trench isolation surrounding a p-FET device having at an overhang portion to overhang the substrate in a direction transverse to a current flow and having a non-overhang portion in a direction parallel to the current flow; and

forming a shallow trench isolation surrounding an n-FET device having at least one overhang portion to overhang the substrate in a direction transverse to a current flow and at least one other overhang portion to overhang the substrate in a direction parallel to the current flow.

11. A method for forming a semiconductor structure, comprising:

forming a shallow trench isolation to surround at least one of an n-FET and a p-FET device with at least one overhang to prevent oxidation induced stress at least in a direction transverse to a direction of a current flow.

12. The method in accordance with claim 11, wherein, for the p-FET device, the at least one overhang is formed transverse to the current flow to prevent performance degradation from compressive stresses.

13. The method in accordance with claim 11, wherein, for the n-FET device, the at least one overhang is formed in a direction parallel to the current flow.

14. The method in accordance with claim 13, wherein, for the n-FET device, the at least one overhang is further formed in a direction transverse to the current flow.