Reduced size stacked semiconductor package and method of making the same

• US 7,847,386 B1
• Filed: 11/05/2007
• Issued: 12/07/2010
• Est. Priority Date: 11/05/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Na, Jae Young, Kim, Bong Chan, Song, Jae Kyu
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US11/935,314
• Time in Patent Office: 1,128 Days
• Field of Search: 257/686, 257/723, 257/777, 257/E25.023, 257/E21.597, 257/E21.598, 257/21.705, 438/109, 438/455
• US Class Current: 257/686
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/08 of an individual bonding area
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73251 on different surfaces
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

In accordance with the present invention, there is provided multiple embodiments of a reduced size stackable semiconductor package. In a basic embodiment of the present invention, the semiconductor package comprises a bulk layer having at least one first bond pad formed therein. At least one active layer is formed on the bulk layer and electrically coupled to the first bond pad. Additionally, at least one second bond pad is formed on the active layer and is electrically coupled thereto. A protection layer is formed on that surface of the active layer having the second bond pad formed thereon, the protection layer also partially encapsulating the second bond pad. In other embodiments of the present invention, the above-described semiconductor package is provided in a stacked arrangement and in a prescribed pattern of electrical communication with one or more additional, identically configured semiconductor packages. In these stacked arrangements, one or more interposers and/or solder balls may optionally integrated into such semiconductor package stacks. In other embodiments of the present invention, a semiconductor package is provided wherein a semiconductor package stack is itself electrically connected to a substrate and covered with an encapsulant material which ultimately hardens into a package body.

Claims

1. A semiconductor package, comprising:

a bulk layer defining opposed, generally planar first and second surfaces and a side surface, the bulk layer having at least one first bond pad formed therein, the first bond pad defining opposed, generally planar first and second surfaces with the first surface of the first bond pad being exposed in and extending in generally co-planar relation to the first surface of the bulk layer, and the second surface of the first bond pad extending in generally co-planar relation to the second surface of the bulk layer;

at least one active layer defining a side surface, the active layer being formed on the bulk layer and electrically connected to the first bond pad;

at least one second bond pad formed on the active layer and electrically connected thereto, the second bond pad defining a generally planar first surface and being separated from the first bond pad by the active layer; and

a protection layer defining a side surface and generally planar first surface which extends in generally co-planar relation to the first surface of the second bond pad, the protection layer being formed on the active layer and at least partially encapsulating the second bond pad formed thereon;

the side surfaces of the bulk layer, the active layer and the protection layer extending in generally co-planar relation to each other.

2. The semiconductor package of claim 1 wherein the semiconductor package comprises a plurality of first bond pads and a plurality of second bond pads which are each electrically connected to the active layer.

3. The semiconductor package of claim 1 wherein the active layer comprises first and second active layers disposed in side by side relation to each other.

4. A semiconductor package, comprising:

at least first and second semiconductor packages, each of which comprises;

a bulk layer having at least one first bond pad formed therein;

at least one active layer formed on the bulk layer and electrically connected to the first bond pad;

at least one second bond pad formed on the active layer and electrically connected thereto, the second bond pad being separated from the first bond pad by the active layer; and

a protection layer formed on the active layer and at least partially encapsulating the second bond pad formed thereon;

the second bond pad of the first semiconductor package being electrically connected to the second bond pad of the second semiconductor package.

5. The semiconductor package of claim 4 wherein the second bond pad of the first semiconductor package and the second bond pad of the second semiconductor package are electrically connected to each other by an intervening interposer.

6. The semiconductor package of claim 5 wherein the interposer comprises:

an insulation layer; and

at least one conductive pad disposed in the insulation layer, the conductive pad being electrically connected to the second bond pads of the first and second semiconductor packages.

7. The semiconductor package of claim 6 wherein:

the first and second semiconductor packages each comprises a plurality of first bond pads and a plurality of second bond pads which are each electrically connected to the active layer thereof;

the interposer comprises a plurality of conductive pads, each of the conductive pads being electrically connected to a corresponding pair of the second bond pads of the first and second semiconductor packages.

8. The semiconductor package of claim 7 wherein:

the first and second semiconductor packages each comprises a plurality of first bond pads and a plurality of second bond pads which are each electrically connected to the active layer thereof;

the second bond pads of the first semiconductor package are electrically connected to respective ones of the second bond pads of the second semiconductor package.

9. The semiconductor package of claim 8 wherein at least some of the first bond pads of the second semiconductor package have solder balls applied thereto.

10. A semiconductor package, comprising:

a substrate comprising an insulation layer defining opposed first and second surfaces, a first conductive pattern disposed on the first surface, and a second conductive pattern disposed on the second surface and electrically connected to the first conductive pattern;

at least one internal semiconductor package electrically connected to the first conductive pattern of the substrate and comprising;

a bulk layer having at least one first bond pad formed therein;

at least one active layer formed on the bulk layer and electrically connected to the first bond pad;

at least one second bond pad formed on the active layer and electrically connected thereto, the second bond pad being separated from the first bond pad by the active layer; and

a protection layer formed on the active layer and at least partially encapsulating the second bond pad formed thereon;

a package body at least partially encapsulating the internal semiconductor package and the substrate such that the package body covers any exposed portions of the first conductive pattern and the first surface of the insulation layer, and does not cover the second conductive pattern.

11. The semiconductor package of claim 10 wherein the at least one internal semiconductor package comprises at least first and second semiconductor packages, each of which comprises:

a bulk layer having at least one first bond pad formed therein;

at least one active layer formed on the bulk layer and electrically connected to the first bond pad;

at least one second bond pad formed on the active layer and electrically connected thereto; and

a protection layer formed on the active layer and at least partially encapsulating the second bond pad formed thereon;

the second bond pad of the first semiconductor package being electrically connected to the second bond pad of the second semiconductor package.

12. The semiconductor package of claim 11 wherein the first bond pad of the second semiconductor package is electrically connected to the first conductive pattern by a conductive bump.

13. The semiconductor package of claim 12 wherein the first bond pad of the first semiconductor package is electrically connected to the first conductive pattern by a conductive wire.

14. The semiconductor package of claim 13 wherein:

the first and second semiconductor packages each comprises a plurality of first bond pads and a plurality of second bond pads which are each electrically connected to the active layer thereof;

the second bond pads of the first semiconductor package are electrically connected to respective ones of the second bond pads of the second semiconductor package;

the first bond pads of the second semiconductor package are electrically connected to the first conductive pattern by conductive bumps; and

the first bond pads of the first semiconductor package are electrically connected to the first conductive pattern by conductive wires.

15. The semiconductor package of claim 11 wherein the second bond pad of the first semiconductor package and the second bond pad of the second semiconductor package are electrically connected to each other by an intervening interposer.

16. The semiconductor package of claim 15 wherein:

the first and second semiconductor packages each comprises a plurality of first bond pads and a plurality of second bond pads which are each electrically connected to the active layer thereof; and

the interposer comprises an insulation layer and a plurality of conductive pads disposed in the insulation layer, each of the conductive pads being electrically connected to a corresponding pair of the second bond pads of the first and second semiconductor packages.

17. A semiconductor package assembly, comprising:

a first semiconductor package, comprising;

an active layer having a plurality of first bond pads arranged therein and electrically coupled thereto;

a bulk layer formed on the active layer and including a plurality of conductive vias which are electrically connected to respective ones of the first bond pads;

a plurality of second bond pads formed on the bulk layer and electrically connected to respective ones of the first bond pads; and

a protection layer formed on the bulk layer and at least partially encapsulating the second bond pads formed thereon

a second semiconductor package, comprising;

an active layer having a plurality of first bond pads electrically coupled thereto;

a bulk layer formed on the active layer and including a plurality of conductive vias which are electrically connected to respective ones of the first bond pads;

a plurality of second bond pads formed on the bulk layer and electrically connected to respective ones of the first bond pads; and

a protection layer formed on the bulk layer and at least partially encapsulating the second bond pads formed thereon;

the first bond pads of the second semiconductor package being electrically connected to respective ones of the first bond pads of the first semiconductor package.

18. The semiconductor package of claim 17 further in combination with:

a substrate having a conductive pattern disposed thereon, at least the second bond pads of the first semiconductor package being electrically connected to the conductive pattern; and

a package body at least partially encapsulating the semiconductor package assembly and the substrate such that at least a portion of the conductive pattern of the substrate is not covered by the package body.

19. The semiconductor package of claim 18 wherein the second bond pads of the first semiconductor package and the second bond pads of the second semiconductor package are each electrically connected to the conductive pattern of the substrate.

20. The semiconductor package of claim 17 wherein the first bond pad of the semiconductor package and the first bond pad of the second semiconductor package are electrically connected to each other by an intervening interposer.