Semiconductor device including leadframe with increased I/O

• US 7,847,392 B1
• Filed: 09/30/2008
• Issued: 12/07/2010
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Choi, Yeon Ho, Kim, GiJeong, Kim, WanJong
• Primary Examiner(s): Smoot; Stephen W
• Application Number:
  US12/242,603
• Time in Patent Office: 798 Days
• Field of Search: 257/E23.047
• US Class Current: 257/696
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/484 Connecting portions
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48639 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48699 Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
• CPC Class Codes: H01L 2224/48739 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48744 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/85439 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/85444 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49551 : characterised by bent parts
• CPC Class Codes: H01L 23/49558 : Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18301 : being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least one row or ring which at least partially circumvents the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die paddle and some of the leads being exposed in a common exterior surface of the package body.

Claims

1. A semiconductor package comprising:

a generally planar die pad defining multiple peripheral edge segments;

a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad;

a plurality of second leads, at least some of which include a downset formed therein, the second leads being segregated into at least two sets which extend along respective ones of at least two peripheral edge segments of the die pad;

a conductive tape layer attached to at least some of the first leads;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second leads, and to the tape layer;

a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first and second leads, the tape layer, and the semiconductor die such that the first and second downsets of the first leads, the downsets of the second leads, and the tape layer are covered by the package body, at least portions of the die pad and the first leads are exposed in and substantially flush with the bottom surface of the package body, and portions of the second leads protrude from at least one of the side surfaces of the package body.

2. The semiconductor package of claim 1 wherein the die pad has a generally quadrangular configuration, and the first and second leads are segregated into at least four sets which each extend along a respective one of the peripheral edge segments of the die pad.

3. The semiconductor package of claim 2 wherein the semiconductor die is electrically connected to the first and second leads and the tape layer by conductive wires which are covered by the package body.

4. The semiconductor package of claim 3 wherein:

each of the first leads includes a first segment, a second segment defining a wire bond zone, and a third segment, the first segment being disposed between the first downset and the die pad and defining a land which is exposed in the bottom surface of the package body, the first downset extending between the first and second segments, and the second downset extending between the second and third segments;

each of the second leads has inner and outer portions, the inner portion of each of the second leads including a first segment which defines a wire bond zone, and a second segment, the downset of each of the second leads extending between the first and second segments thereof;

the tape layer is attached to the first segments of at least some of the first leads; and

the conductive wires extend from the semiconductor die to respective ones of the wire bond zones of the first and second leads, and to the tape layer.

5. The semiconductor package of claim 4 wherein the first segment of each of the first leads includes a top surface, a bottom surface which defines the land, a first surface which is recessed relative to the bottom surface and covered by the package body, and a second surface which is recessed relative to the bottom surface and covered by the package body, the land being disposed between the first and second surfaces, with the tape layer being attached to the top surfaces of at least some of the first segments.

6. The semiconductor package of claim 4 wherein the die pad further includes a plurality of pads integrally connected to and extending perpendicularly from at least one of the peripheral edge segments thereof, the tape layer further being attached to at least some of the pads.

7. The semiconductor package of claim 6 wherein:

the die pad defines opposed, generally planar top and bottom surfaces;

each of the pads has a top surface which extends in generally coplanar relation to the top surface of the die pad and a bottom surface which is recessed relative to the bottom surface of the die pad;

each of the pads is covered by the package body; and

the tape layer is attached to the top surfaces of at least some of the pads and a peripheral portion of the top surface of the die pad.

8. The semiconductor package of claim 7 wherein the die pad includes a first surface which is recessed relative to the bottom surface thereof and is generally coplanar with the bottom surfaces of the pads, the first surface of the die pad being covered by the package body.

9. The semiconductor package of claim 7 wherein the pads are segregated into at least four sets which extend from respective ones of the peripheral edge segments of the die pad.

10. The semiconductor package of claim 9 wherein a portion of the first segment of each of the first leads is disposed between an adjacent pair of the pads.

11. The semiconductor package of claim 6 wherein:

the die pad, the pads, and the first segments of the first leads extend along a first plane;

the wire bond zones of the first and second leads each extend along a second plane which is disposed in spaced, generally parallel relation to the first plane; and

the third segments of the first leads, the second segments of the inner portions of the second leads, and the outer portions of the second leads each extend along a third plane which is disposed in spaced, generally parallel relation to the second plane such that the second plane extends between the first and third planes.

12. The semiconductor package of claim 1 wherein the tape layer comprises:

an adhesive layer attached to at least some of the first leads;

an insulating layer disposed on the adhesive layer;

a metal layer disposed on the insulating layer; and

a plating layer disposed on the metal layer, the semiconductor die being electrically connected to the plating layer.

13. A semiconductor package comprising:

a die pad;

a plurality of pads integrally connected to and extending from the die pad;

a plurality of first leads which each include first and second downsets formed therein in spaced relation to each other, the first leads extending along the die pad;

a plurality of second leads, at least some of which include a downset formed therein, the second leads extending along the die pad;

a conductive tape layer attached to at least some of the first leads and at least some of the pads;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second leads, and to the tape layer; and

a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the pads, the first and second leads, the tape layer, and the semiconductor die such that the pads, the first and second downsets of the first leads, the downsets of the second leads, and the tape layer are covered by the package body, at least portions of the first leads are exposed in the bottom surface of the package body, and portions of the second leads protrude from the side surface of the package body.

14. The semiconductor package of claim 13 wherein:

each of the first leads includes a first segment, a second segment which defines a wire bond zone, and a third segment, the first segment being disposed between the first downset and the die pad and defining a land which is exposed in the bottom surface of the package body, the first downset extending between the first and second segments, and the second downset extending between the second and third segments;

each of the second leads has inner and outer portions, the inner portion of each of the second leads including a first segment which defines a wire bond zone, and a second segment, the downset of each of the second leads extending between the first and second segments thereof;

the tape layer is attached to the first segments of at least some of the first leads; and

the conductive wires extend from the semiconductor die to respective ones of the wire bond zones of the first and second leads, and to the tape layer.

15. The semiconductor package of claim 14 wherein the first segment of each of the first leads includes a top surface, a bottom surface which defines the land, a first surface which is recessed relative to the bottom surface and covered by the package body, and a second surface which is recessed relative to the bottom surface and covered by the package body, the land being disposed between the first and second surfaces, with the tape layer being attached to the top surfaces of at least some of the first segments.

16. The semiconductor package of claim 14 wherein:

the die pad defines opposed, generally planar top and bottom surfaces;

each of the pads has a top surface which extends in generally coplanar relation to the top surface of the die pad and a bottom surface which is recessed relative to the bottom surface of the die pad; and

the tape layer is attached to the top surfaces of at least some of the pads and a peripheral portion of the top surface of the die pad.

17. The semiconductor package of claim 16 wherein the die pad includes a first surface which is recessed relative to the bottom surface thereof and is generally coplanar with the bottom surfaces of the pads, the first surface of the die pad being covered by the package body.

18. The semiconductor package of claim 14 wherein a portion of the first segment of each of the first leads is disposed between an adjacent pair of the pads.

19. The semiconductor package of claim 13 wherein the tape layer comprises:

an adhesive layer attached to at least some of the first leads;

an insulating layer disposed on the adhesive layer;

a metal layer disposed on the insulating layer; and

a plating layer disposed on the metal layer, the semiconductor die being electrically connected to the plating layer.

20. A semiconductor package comprising:

a die pad;

a plurality of pads integrally connected to and extending from the die pad;

a plurality of first leads which each include first and second downsets formed therein and define a wire bond zone between the first and second downsets, the first leads extending along the die pad;

a plurality of second leads, at least some of which include a downset formed therein, the second leads extending along the die pad, with at least some of the second leads defining a wire bond zone between the downset thereof and the die pad;

a semiconductor die attached to the die pad and electrically connected to at least one of each of the first and second leads; and

a package body defining a bottom surface, the package body at least partially encapsulating the pads, the first and second leads, and the semiconductor die such that the pads, the first and second downsets of the first leads and the downsets of the second leads are covered by the package body, at least portions of the die pad and the first leads are exposed in the bottom surface of the package body, and portions of the second leads are exposed in the package body.