Test apparatus and performance board

• US 7,847,573 B2
• Filed: 11/29/2007
• Issued: 12/07/2010
• Est. Priority Date: 03/17/2006
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Ohashi, Masatoshi
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Chan; Emily Y
• Application Number:
  US11/946,870
• Publication Number:
  US 20090261841A1
• Time in Patent Office: 1,104 Days
• Field of Search: 324537-765, 714738-744, 702118-124
• US Class Current: 324/756.05
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: G01R 31/31703 Comparison aspects, e.g. signature analysis, comparators concerning scan tests G01R31/318566; concerning testers G01R31/3193
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31932 Comparators

Abstract

Provided is a test apparatus for testing a device under test, including: a plurality of signal supply sections that output test signals at different timing from each other; and a connection section that connects lines of wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the lines of wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals. The connection section may include a performance board to which the device under test is mounted, where the lines of wiring are connected with each other on the performance board.

Claims

1. A test apparatus for testing a device under test, comprising:

a plurality of signal supply sections that output test signals at different timing from each other;

a connection section that connects lines of individual wiring transmitting the test signals respectively outputted from the signal supply sections with each other, connects the connected lines of individual wiring to an input terminal of the device under test, and inputs the test signals to the input terminal after superposing the test signals;

a plurality of waveform shapers provided for the signal supply sections respectively, each of the waveform shapers generating a test signal to be supplied to a corresponding one of the signal supply sections, based on given pattern data; and

a plurality of pattern generating sections provided for the waveform shapers respectively, each of the pattern generating sections supplying the pattern data to a corresponding one of the waveform shapers, wherein

each of the pattern generating sections includes a plurality of pattern generating circuits that generate the pattern data to be given to a corresponding one of the waveform shapers by an interleave technique.

2. The test apparatus as set forth in claim 1, wherein

the connection section includes a performance board to which the device under test is mounted, and

the lines of individual wiring are connected with each other on the performance board, and are connected to the input terminal of the device under test.

3. The test apparatus as set forth in claim 2, wherein

the connection section further includes shared wiring that is provided on the performance board and whose one end is connected to the input terminal of the device under test, and

each of the lines of individual wiring is connected to the other end of the shared wiring.

4. The test apparatus as set forth in claim 3, wherein

a line length of the shared wiring is shorter than a line length of each of the lines of individual wiring on the performance board.

5. The test apparatus as set forth in claim 4, wherein

the line length of each of the lines of individual wiring on the performance board is substantially the same as each other.

6. The test apparatus as set forth in claim 3, wherein

the shared wiring is connected to a clock input terminal of the device under test.

7. The test apparatus as set forth in claim 1, wherein

each of the signal supply sections outputs a signal fixed to a predetermined voltage value, which determines a reference potential of the test signal inputted to the device under test, to the connection section while another of the signal supply sections is outputting a test signal.

8. The test apparatus as set forth in claim 7, wherein

an output impedance of each of the signal supply sections is substantially the same as a characteristic impedance of the individual wiring.

9. The test apparatus as set forth in claim 1, wherein

the waveform shapers are a first waveform shaper and a second waveform shaper, which operate in synchronization with a predetermined test period, where the first waveform shaper outputs a test signal in the first half of each test period, and the second waveform shaper outputs a test signal in the last half of each test period.

10. The test apparatus as set forth in claim 9, wherein

each of the pattern generating sections stores pattern data of a test signal to be outputted by a corresponding one of the waveform shapers, in the order in which the pattern data is to be outputted.

11. The test apparatus as set forth in claim 9, wherein

the first waveform shaper and the second waveform shaper output a test signal in accordance with a given clock signal, and the test apparatus further comprises:

a timing control section that supplies the clock signal to the first waveform shaper in the first half of the test period, and supplies the clock signal to the second waveform shaper in the last half of the test period.

12. The test apparatus as set forth in claim 1, further comprising:

a pattern setting section that sets a pattern to be generated by each of the pattern generating circuits, so that the pattern data to be given to each of the waveform shapers is generated by a corresponding one of the pattern generating circuits by an interleave technique.

13. The test apparatus as set forth in claim 1, wherein

the signal supply sections are a first signal supply section and a second signal supply section, and

the first signal supply section and the second signal supply section generate a test signal having an amplitude that is substantially twice an amplitude of a signal to be inputted to the device under test.

14. The test apparatus as set forth in claim 1, wherein the signal supply section includes a driver.