Three dimensional NAND memory
First Claim
Patent Images
1. A monolithic, three dimensional NAND string, comprising:
- a first memory cell located over a second memory cell;
a select transistor;
a first word line of the first memory cell;
a second word line of the second memory cell;
a bit line;
a source line; and
a select gate line of the select transistor;
wherein;
the first and the second word lines are not parallel to the bit line;
the first and the second word lines extend parallel to at least one of the source line and the select gate line;
the NAND string is formed vertically over a substrate;
the select transistor is located in a trench in the substrate, the trench extending substantially parallel to the select gate line of the select transistor.
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Abstract
A monolithic, three dimensional NAND string includes a first memory cell located over a second memory cell, a select transistor, a first word line of the first memory cell, a second word line of the second memory cell, a bit line, a source line, and a select gate line of the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line.
257 Citations
13 Claims
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1. A monolithic, three dimensional NAND string, comprising:
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a first memory cell located over a second memory cell; a select transistor; a first word line of the first memory cell; a second word line of the second memory cell; a bit line; a source line; and a select gate line of the select transistor; wherein; the first and the second word lines are not parallel to the bit line; the first and the second word lines extend parallel to at least one of the source line and the select gate line; the NAND string is formed vertically over a substrate; the select transistor is located in a trench in the substrate, the trench extending substantially parallel to the select gate line of the select transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A monolithic, three dimensional NAND string, comprising:
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a first memory cell located over a second memory cell; a select transistor; a first word line of the first memory cell; a second word line of the second memory cell; a bit line; a source line; and a select gate line of the select transistor; wherein; the first and the second word lines are not parallel to the bit line; the first and the second word lines extend parallel to at least one of the source line and the select gate line; the NAND string is formed vertically over a substrate; the select transistor is located on a substrate or in a trench in the substrate; the first memory cell is located in a first device level; the second memory cell is located in a second device level located on the select transistor and below the first device level; a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell; the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor; a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line; a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line; the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions; the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions; the semiconductor active region of the select transistor comprises a third pillar; one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar; the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar. - View Dependent Claims (9, 10, 11, 12, 13)
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Specification
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Current AssigneeSanDisk Technologies LLC (Western Digital Corporation)
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Original AssigneeSanDisk 3D LLC (Western Digital Corporation)
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InventorsMokhlesi, Nima, Scheuerlein, Roy
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Primary Examiner(s)HUR, JUNG H
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Application NumberUS11/691,901Publication NumberTime in Patent Office1,351 DaysField of Search365/185.05, 365/185.17, 365/51, 365/63, 365/72, 257/278, 257/E21.614, 257/E27.026US Class Current365/185.17CPC Class CodesG11C 16/0483 comprising cells having sev...H01L 29/792 with charge trapping gate i...H01L 29/7926 Vertical transistors, i.e. ...H10B 43/20 characterised by three-dime...H10B 43/27 the channels comprising ver...H10B 43/30 characterised by the memory...
