Non-volatile memory systems and methods including page read and/or configuration features
First Claim
Patent Images
1. A method comprising:
- reading a fuse non-volatile memory location for configuration data in response to a page read command;
storing said configuration data in a volatile memory location; and
performing a page read sequence for a memory in association with the configuration data.
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Abstract
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
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Citations
43 Claims
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1. A method comprising:
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reading a fuse non-volatile memory location for configuration data in response to a page read command; storing said configuration data in a volatile memory location; and performing a page read sequence for a memory in association with the configuration data. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 31, 32, 33, 34, 35, 39, 40)
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2. A method comprising:
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reading a fuse non-volatile memory location for configuration data in response to a page program command; storing said configuration data in a volatile memory location; and performing a page programming sequence for a memory in association with the configuration data. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 26, 27, 28, 29, 30, 36, 37, 38, 41, 42)
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22. The method of 2 further comprising:
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coupling a reference array to reference memory subarrays; and providing stored reference signals used for programming reference memory cells, the stored reference signals corresponding to detected reference signals.
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43. A method comprising:
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reading a fuse non-volatile memory location for configuration data in response to a page read command; storing said configuration data in a volatile memory location; and providing chip operating settings for a page read sequence for a memory as a function of the configuration data.
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Specification