Nonvolatile semiconductor memory

• US 7,848,170 B2
• Filed: 03/20/2009
• Issued: 12/07/2010
• Est. Priority Date: 07/25/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiura, Yoshihisa
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US12/407,938
• Publication Number:
  US 20100020628A1
• Time in Patent Office: 627 Days
• Field of Search: 365/226, 365/230.06, 365/189.09, 365/189.08, 365/194
• US Class Current: 365/226
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.

Claims

1. A nonvolatile semiconductor memory comprising:

a first memory chip set so as to be operated by specifying the chip address upon reset; and

a second memory chip set so as not to be specified by the chip address and not to be operated upon reset,

the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value,

the power-on reset circuit including;

a first voltage dividing resistor having one end connected to a power supply;

a second voltage dividing resistor connected between an other end of the first voltage dividing resistor and ground;

a PMOS transistor having a source connected to the power supply and a gate fed with a voltage corresponding to a voltage on a first contact between the first voltage dividing resistor and the second voltage dividing resistor;

an output resistor connected between a drain of the PMOS transistor and the ground;

a switch element connected between the power supply and the first contact;

a voltage dividing ratio adjusting resistor connected in series with the switch element between the power supply and the first contact;

a switching circuit which outputs a switching signal for switching on/off the switch element; and

an output terminal connected to a second contact between the PMOS transistor and the output resistor to output the reset signal,

wherein in the power-on reset circuit of the first memory chip, the switching circuit turns on the switch element, and

in the power-on reset circuit of the second memory chip, the switching circuit turns off the switch element.

2. The nonvolatile semiconductor memory of claim 1, wherein the switching circuit switches on/off the switch element based on the chip address.

3. The nonvolatile semiconductor memory of claim 1, wherein the first memory chip and the second memory chip are NAND flash memory chips.

4. The nonvolatile semiconductor memory of claim 2, wherein the first memory chip and the second memory chip are NAND flash memory chips.

5. The nonvolatile semiconductor memory of claim 1, wherein the switch element is a transistor.

6. The nonvolatile semiconductor memory of claim 2, wherein the switch element is a transistor.

7. The nonvolatile semiconductor memory of claim 3, wherein the switch element is a transistor.

8. A nonvolatile semiconductor memory comprising:

a first memory chip set so as to be operated by specifying the chip address upon reset; and

a second memory chip set so as not to be specified by the chip address and not to be operated upon reset,

the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value,

the power-on reset circuit including;

a first voltage dividing resistor having one end connected to a power supply;

a second voltage dividing resistor connected between an other end of the first voltage dividing resistor and ground;

a PMOS transistor having a source connected to the power supply and a gate fed with a voltage corresponding to a voltage on a first contact between the first voltage dividing resistor and the second voltage dividing resistor;

an output resistor connected between a drain of the PMOS transistor and the ground;

a switch element connected between the ground and the first contact;

a voltage dividing ratio adjusting resistor connected in series with the switch element between the ground and the first contact;

a switching circuit which outputs a switching signal for switching on/off the switch element; and

an output terminal connected to a second contact between the PMOS transistor and the output resistor to output the reset signal,

wherein in the power-on reset circuit of the first memory chip, the switching circuit turns off the switch element, and

in the power-on reset circuit of the second memory chip, the switching circuit turns on the switch element.

9. The nonvolatile semiconductor memory of claim 8, wherein the switching circuit switches on/off the switch element based on the chip address.

10. The nonvolatile semiconductor memory of claim 8, wherein the first memory chip and the second memory chip are NAND flash memory chips.

11. The nonvolatile semiconductor memory of claim 9, wherein the first memory chip and the second memory chip are NAND flash memory chips.

12. The nonvolatile semiconductor memory of claim 8, wherein the switch element is a transistor.

13. The nonvolatile semiconductor memory of claim 9, wherein the switch element is a transistor.

14. The nonvolatile semiconductor memory of claim 10, wherein the switch element is a transistor.

15. A nonvolatile semiconductor memory comprising:

a first memory chip set so as to be operated by specifying the chip address upon reset; and

a second memory chip set so as not to be specified by the chip address and not to be operated upon reset,

the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value,

the power-on reset circuit including;

a first voltage dividing resistor having one end connected to a power supply;

a second voltage dividing resistor connected between an other end of the first voltage dividing resistor and ground;

a PMOS transistor having a source connected to the power supply and a gate fed with a voltage corresponding to a voltage on a first contact between the first voltage dividing resistor and the second voltage dividing resistor;

an output resistor connected between a drain of the PMOS transistor and the ground;

a switch element connected between the ground and the first contact;

a voltage dividing ratio adjusting resistor connected in series with the switch element between the ground and the first contact;

a switching circuit which outputs a switching signal for switching on/off the switch element; and

an output terminal connected to a second contact between the PMOS transistor and the output resistor to output the reset signal,

wherein in the power-on reset circuit of the first memory chip, the switching circuit turns off the switch element, and

in the power-on reset circuit of the second memory chip, the switching circuit turns off the switch element when the power supply voltage is lower than a set voltage, and the switching circuit turns on the switch element when the power supply voltage is equal to or higher than the set voltage.

16. The nonvolatile semiconductor memory of claim 15, wherein the switching circuit switches on/off the switch element based on the chip address.

17. The nonvolatile semiconductor memory of claim 15, wherein the first memory chip and the second memory chip are NAND flash memory chips.

18. The nonvolatile semiconductor memory of claim 16, wherein the first memory chip and the second memory chip are NAND flash memory chips.

19. The nonvolatile semiconductor memory of claim 15, wherein the switch element is a transistor.

20. The nonvolatile semiconductor memory of claim 16, wherein the switch element is a transistor.