Memory circuit having reduced power consumption

• US 7,848,172 B2
• Filed: 11/24/2008
• Issued: 12/07/2010
• Est. Priority Date: 11/24/2008
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Dudeck, Dennis E., Wozniak, Ronald James, Evans, Donald Albert, Pham, Hai Quang, Werner, Wayne E.
• Primary Examiner(s): Mai; Son L
• Application Number:
  US12/276,576
• Publication Number:
  US 20100128549A1
• Time in Patent Office: 743 Days
• Field of Search: 365/226, 365/227
• US Class Current: 365/227
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

Claims

1. A memory circuit, comprising:

a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells;

a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and

a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays;

wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.

2. The memory circuit of claim 1, further comprising a switching circuit connected to each of the memory sub-arrays and to at least a first power connection adapted to convey a first supply voltage supplied to the memory circuit, the switching circuit being operative to selectively individually connect at least one of the respective memory sub-arrays to or selectively individually disconnect at least one of the respective memory sub-arrays from the first power connection as a function of at least one control signal supplied to the switching circuit.

3. The memory circuit of claim 2, wherein the switching circuit comprises:

a first transistor comprising a first source/drain coupled to a first one of the memory sub-arrays, a second source/drain coupled to the first power connection, and a gate adapted for receiving a first control signal, the first transistor being operative to selectively connect the first memory sub-array to the first power connection as a function of the first control signal; and

at least a second transistor comprising a first source/drain coupled to a second one of the memory sub-arrays, a second source/drain coupled to the first power connection, and a gate adapted for receiving a second control signal, the second transistor being operative to selectively connect the second memory sub-array to the first power connection as a function of the second control signal.

4. The memory circuit of claim 3, wherein the first control signal being in a first state affects the first supply voltage to be applied to the first memory sub-array, and the first control signal being in a second state affects the first supply voltage to be withheld from the first memory sub-array, and wherein the second control signal being in the first state affects the first supply voltage to be applied to the second memory sub-array, and the second control signal being in the second state affects the first supply voltage to be withheld from the second memory sub-array.

5. The memory circuit of claim 3, wherein the power control circuit is operative to generate the first and the second control signals as a function of a composite control signal received by the power control circuit, wherein the composite control signal being in a first state affects the first supply voltage to be applied to the first memory sub-array, the composite control signal being in a second state affects the first supply voltage to be withheld from the first memory sub-array, the composite control signal being in a third state affects the first supply voltage to be applied to the second memory sub-array, and the composite control signal being in a fourth state affects the first supply voltage to be withheld from the second memory sub-array.

6. The memory circuit of claim 5, wherein the power control circuit comprises a plurality of transistors configured to conduct less power than the first and second transistors in the switching circuit.

7. The memory circuit of claim 5, wherein the composite power control signal comprises a serial signal.

8. The memory circuit of claim 1, wherein at least a first one of the plurality of memory sub-arrays comprises a volatile memory and at least a second one of the plurality of memory sub-arrays comprises a non-volatile memory.

9. The memory circuit of claim 8, wherein the volatile memory comprises at least one of static random access memory cells and dynamic random access memory cells, and wherein the non-volatile memory comprises at least one of flash memory cells, phase change memory cells, one time programmable memory cells, few times programmable memory cells, and read-only memory cells.

10. The memory circuit of claim 1, wherein at least a first one of the plurality of memory sub-arrays comprises a first type of volatile memory and at least a second one of the plurality of memory sub-arrays comprises a second type of volatile memory.

11. The memory circuit of claim 1, wherein at least a first one of the plurality of memory sub-arrays comprises a first type of non-volatile memory and at least a second one of the plurality of memory sub-arrays comprises a second type of non-volatile memory.

12. The memory circuit of claim 1, wherein the row circuit in at least a given one of the memory sub-arrays comprises a row address decoder and at least one row driver coupled to the row address decoder and to at least one corresponding row line in the given memory sub-array, and wherein the column circuit in the given memory sub-array comprises a column address decoder and at least one sense amplifier coupled to the column address decoder and to at least one corresponding column line in the given memory sub-array.

13. The memory circuit of claim 1, wherein the shared circuit comprises at least one of a voltage regulator, a control circuit, a delay circuit, a timing circuit, a digital circuit, an analog circuit, a redundancy circuit, a built-in-self-test circuit, a built-in-self-repair circuit, an input buffer and an output buffer.

14. The memory circuit of claim 1, wherein the shared circuit comprises a built-in-self-test circuit operative to test the memory circuit with at least one of the plurality of memory sub-arrays powered and at least one of the memory sub-arrays unpowered.

15. The memory circuit of claim 1, wherein at least one of the plurality of memory sub-arrays comprises at least one of a single-port memory, a dual-port memory, a multi-port memory, and a content-addressable memory.

16. An integrated circuit including at least one memory circuit, the at least one memory circuit comprising:

a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuit being operative to provide selective access to one or more of the memory cells;

a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and

a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays;

wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.

17. The integrated circuit of claim 16, wherein the at least one memory circuit further comprises a switching circuit connected to each of the memory sub-arrays and to at least a first power connection adapted to convey a first supply voltage supplied to the memory circuit, the switching circuit being operative to selectively individually connect at least one of the respective memory sub-arrays to or selectively individually disconnect at least one of the respective memory sub-arrays from the first power connection as a function of at least one control signal supplied to the switching circuit.

18. The integrated circuit of claim 17, wherein the switching circuit comprises:

a first transistor comprising a first source/drain coupled to a first one of the memory sub-arrays, a second source/drain coupled to the first power connection, and a gate adapted for receiving a first control signal, the first transistor being operative to selectively connect the first memory sub-array to the first power connection as a function of the first control signal; and

at least a second transistor comprising a first source/drain coupled to a second one of the memory sub-arrays, a second source/drain coupled to the first power connection, and a gate adapted for receiving a second control signal, the second transistor being operative to selectively connect the second memory sub-array to the first power connection as a function of the second control signal.

19. The integrated circuit of claim 18, wherein the power control circuit is operative to generate the first and the second control signals as a function of a composite control signal received by the power control circuit, wherein the composite control signal being in a first state affects the first supply voltage to be applied to the first memory sub-array, the composite control signal being in a second state affects the first supply voltage to be withheld from the first memory sub-array, the composite control signal being in a third state affects the first supply voltage to be applied to the second memory sub-array, and the composite control signal being in a fourth state affects the first supply voltage to be withheld from the second memory sub-array.

20. An electronic system, comprising:

at least one integrated circuit including at least one embedded memory circuit, the at least one embedded memory circuit comprising;

a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells;

a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the embedded memory circuit; and

a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays;

wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.