Memory circuit having reduced power consumption
First Claim
1. A memory circuit, comprising:
- a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells;
a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and
a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays;
wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.
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Accused Products
Abstract
A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.
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Citations
20 Claims
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1. A memory circuit, comprising:
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a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells; a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays; wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit including at least one memory circuit, the at least one memory circuit comprising:
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a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuit being operative to provide selective access to one or more of the memory cells; a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the memory circuit; and a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays; wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered. - View Dependent Claims (17, 18, 19)
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20. An electronic system, comprising:
at least one integrated circuit including at least one embedded memory circuit, the at least one embedded memory circuit comprising; a plurality of memory sub-arrays, each of the memory sub-arrays including at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits, the row and column circuits being operative to provide selective access to one or more of the memory cells; a shared circuit coupled to each of the memory sub-arrays, the shared circuit comprising circuitry, external to the plurality of memory sub-arrays, which is operative to control one or more functions of the plurality of memory sub-arrays as a function of at least one control signal supplied to the embedded memory circuit; and a power control circuit external to the shared circuit and to the plurality of memory sub-arrays, the power control circuit being operative to individually control application of power to the plurality of memory sub-arrays; wherein the memory circuit is operative, with at least one of the plurality of memory sub-arrays operative, with one or more of the plurality of memory sub-arrays powered and concurrently with one or more of the plurality of memory sub-arrays unpowered.
Specification