Video and graphics system with an MPEG video decoder for concurrent multi-row decoding

• US 7,848,430 B2
• Filed: 05/15/2007
• Issued: 12/07/2010
• Est. Priority Date: 11/09/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Bhatia, Sandeep, Valmiki, Ramanujan K.
• Primary Examiner(s): Sajous; Wesner
• Application Number:
  US11/748,948
• Publication Number:
  US 20070217518A1
• Time in Patent Office: 1,302 Days
• Field of Search: 348/420, 348/423, 348/425, 348/430, 348/490, 348/492, 348567-568, 545/547, 545/555, 545/556, 545/560, 545/567, 370391-392, 370/396, 375/240.23, 375/240.25, 375/240.28, 375/246, 375/316, 375/136, 375/147, 375/240.24, 455/547, 455/555, 455/556, 455/560, 455/567
• US Class Current: 375/240.24
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2340/06 Colour space transformation
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 : Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 7/00 : Television systems details H04N3/00, H04N5/00; methods or arrangements, for coding, decoding, compressing or decompressing digital video signals H04N19/00; selective content distribution H04N21/00
• CPC Class Codes: H04N 7/0135 : involving interpolation processes interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers
• CPC Class Codes: Y10S 502/506 : Method of making inorganic composition utilizing organic compound, except formic, acetic, or oxalic acid or salt thereof

Abstract

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video data. The video decoder includes multiple row decoding engines for decoding the MPEG-2 video data. Each row decoding engine concurrently decodes two or more rows of the MPEG-2 video data. The row decoding engines have a pipelined architecture for concurrently decoding multiple rows of MPEG-2 video data. The video decoder may be integrated on an integrated circuit chip with other video and graphics system components such as transport processors for receiving one or more compressed data streams and for extracting video data, and a video compositor for blending processed video data with graphics.

Claims

1. A method of decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said method comprising:

decoding the header of at least one macrblock using a first processing element; and

decoding the block layer data of said at least one macroblock using a second processing element; and

wherein the at least one macroblock comprises a first row of macroblocks of a frame.

2. The method of claim 1, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

3. The method of claim 2, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

4. The method of claim 1, wherein the at least one block comprises block layer data from the first row of macroblocks.

5. The method of claim 4, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

6. The method of claim 5, wherein the second mprocessing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

7. The method of claim 1, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

8. The method of claim 4, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

45. The method of claim 1, further comprising:

decoding block layer data for at least another macroblock using the second processing element while decoding the macroblock level header for the at least one macroblock with the first processing element, wherein said macroblock level header is hierarchically higher than the block layer data.

9. A method of decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said method comprising:

decoding the header of at least one macrblock using a first processing element; and

decoding the block layer data of said at least one macroblock using a second processing element;

wherein the at least one macroblock comprises a first row of macroblocks of a frame;

wherein the at least one block comprises block layer data from the first row of macroblocks; and

wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

10. The method of claim 9, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

11. The method of claim 10, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

12. The method of claim 9, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

13. The method of claim 12, wherein the second mprocessing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

14. The method of claim 9, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

15. The method of claim 9, wherein decoding block layer data for at least another macroblock using the second processing element while decoding the header at the at least one macroblock with the first processing element.

16. A circuit for decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said circuit comprising:

a first processing element for decoding the header of at least one macrblock; and

a second processing element for decoding the block layer data of said at least one macroblock using; and

wherein the at least one macroblock comprises a first row of macroblocks of a frame.

17. The circuit of claim 16, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

18. The circuit of claim 17, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

19. The circuit of claim 16, wherein the at least one block comprises block layer data from the first row of macroblocks.

20. The circuit of claim 19, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

21. The circuit of claim 20, wherein the second processing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

22. The circuit of claim 20, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

23. The circuit of claim 19, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

46. The circuit of claim 16, wherein decoding block layer data for at least another macroblock using the second processing element while decoding the macroblock level header for the at least one macroblock with the first processing element, wherein said macroblock level header is hierarchically higher than the block layer data.

24. A circuit of decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said circuit comprising:

a first processing element for decoding the header of at least one macrblock; and

a second processing element for decoding the block layer data of said at least one macroblock using a second processing element;

wherein the at least one macroblock comprises a first row of macroblocks of a frame; and

wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

25. The circuit of claim 24, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

26. The circuit of claim 25, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

27. The circuit of claim 24, wherein the at least one block comprises block layer data from the first row of macroblocks.

28. The circuit of claim 27, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

29. The circuit of claim 28, wherein the second processing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

30. The circuit of claim 27, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

31. A circuit for decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said circuit comprising:

a first processing element for decoding the header of at least one macrblock; and

a second processing element for decoding the block layer data of said at least one macroblock using a second processing element;

wherein the at least one macroblock comprises a first row of macroblocks of a frame;

wherein the at least one block comprises block layer data from the first row of macroblocks; and

wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

32. The circuit of claim 31, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

33. The circuit of claim 32, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

34. The circuit of claim 31, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

35. The circuit of claim 34, wherein the second mprocessing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

36. The circuit of claim 31, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

37. The circuit of claim 31, wherein decoding block layer data for at least another macroblock using the second processing element while decoding the header at the at least one macroblock with the first processing element.

38. A method of decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said circuit comprising:

decoding the header of at least one macrblock with a first processing element; and

decoding the block layer data of said at least one macroblock using a second processing element;

wherein the at least one macroblock comprises a first row of macroblocks of a frame; and

wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

39. The method of claim 38, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

40. The method of claim 39, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

41. The method of claim 38, wherein the at least one block comprises block layer data from the first row of macroblocks.

42. The method of claim 41, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

43. The method of claim 42, wherein the second processing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

44. The method of claim 41, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

47. A method of decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said method comprising:

decoding the header of at least one macrblock using a first processing element;

decoding the block layer data of said at least one macroblock using a second processing element; and

decoding block layer data for at least another macroblock using the second processing element while decoding the macroblock level header for the at least one macroblock with the first processing element, wherein said macroblock level header is hierarchically higher than the block layer data.

48. The method of claim 47, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

49. The method of claim 48, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

50. The method of claim 47, wherein the at least one block comprises block layer data from the first row of macroblocks.

51. The method of claim 50, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

52. The method of claim 51, wherein the second mprocessing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

53. The method of claim 47, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

54. The method of claim 50, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.

55. A circuit for decoding MPEG data comprising a plurality of macroblocks, each macroblock comprising a header and block layer data, said circuit comprising:

a first processing element for decoding the header of at least one macrblock; and

a second processing element for decoding the block layer data of said at least one macroblock using; and

wherein decoding block layer data for at least another macroblock using the second processing element while decoding the macroblock level header for the at least one macroblock with the first processing element, wherein said macroblock level header is hierarchically higher than the block layer data.

56. The circuit of claim 55, wherein the block layer data of said at least one macroblock is decoded by the second processing element after the first processing element decodes the header of the at least one macroblock.

57. The circuit of claim 56, wherein the block layer data of said at least one macroblock is decoded by the second processing element immediately after the first processing element decodes the header of the at least one macroblock.

58. The circuit of claim 55, wherein the at least one block comprises block layer data from the first row of macroblocks.

59. The circuit of claim 58, wherein the second processing element decodes the block layer data of said block layer data from the first row of macroblocks after the first processing element decodes the header of the first row of macroblocks.

60. The circuit of claim 59, wherein the second processing element decodes the block layer of data of said block layer data from the first row of macroblocks immediately after the first processing element decodes the header of the first row of macroblocks.

61. The circuit of claim 59, wherein the second processing element decodes a second row of block data of a second row of macroblocks while the first processing element decodes the headers of the first row of macroblocks.

62. The circuit of claim 58, wherein the first processing element decodes a third row of macroblock header data while the second processing element decodes the block layer data from the first row of macroblocks.