Memory controller with ring bus for interconnecting memory clients to memory devices

• US 7,849,256 B2
• Filed: 07/11/2006
• Issued: 12/07/2010
• Est. Priority Date: 07/11/2006
• Status: Active Grant

• Current Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Miretsky, Alexander, Law, Patrick, Kruger, Warren F.
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Lo; Kenneth M
• Application Number:
  US11/484,191
• Publication Number:
  US 20080016254A1
• Time in Patent Office: 1,610 Days
• Field of Search: 711/105, 711/158, 711/151
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1657 Access to multiple memories

Abstract

Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller.

Claims

1. An integrated circuit device comprising:

a central memory controller circuit coupled to at least one read bus switch and each of the one or more memory clients, and configured to route the memory request to the target memory device, wherein the memory controller circuit comprises,

a switch matrix configured to transmit the memory requests from the requesting memory client to the target memory device;

an arbiter circuit coupling each memory client of the one or more memory clients to a respective memory channel;

a sequencer circuit coupling each arbiter to a respective read bus switch corresponding to the requesting memory client; and

a client interface coupling the arbiter circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client;

a plurality of memory clients operable to send or receive data to one or more memory devices by sending memory access requests to the central memory controller circuit; and

a ring bus connected between pairs of read bus switches of a plurality of read bus switches, and configured to transmit a memory read transfer between the target memory device and a requesting memory client, wherein the ring bus comprises a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography.

2. The integrated circuit device of claim 1, wherein the bus comprises a plurality of segments, and wherein each segment interconnects a pair of memory control circuits together.

3. The integrated circuit device of claim 1, wherein each memory control circuit includes a memory interface, and wherein the memory devices comprise a dynamic random access memory device separate from the integrated circuit device coupled to a respective memory interface of the plurality of the memory control circuits.

4. The integrated circuit device of claim 3, wherein

the memory client is configured to transmit a read request signal to a target memory device and receive a data read signal from the target memory device in response to the read request signal from the memory client;

and

the memory client is configured to transmit a write request signal to the target memory device and receive a write acknowledge signal from the target memory device in response to the write request signal from the memory client.

5. The integrated circuit device of claim 4, wherein the ring bus is used to transmit the read data signal from the target memory device to the memory client.

6. The integrated circuit device of claim 5, wherein the ring bus is used to transmit the read request signal from the memory client to the target memory device.

7. The integrated circuit device of claim 6, wherein the ring bus is used to transmit the write request signal from the memory client to the target memory device.

8. The integrated circuit device of claim 7, wherein the ring bus is used to transmit the write acknowledge signal from the target memory device to the memory client.

9. The integrated circuit device of claim 8, wherein the ring bus comprises a respective virtual channel for each of the read data, read request, write request and write acknowledge signals to avoid deadlock among each of the read data, read request, write request, and write acknowledge signal types.

10. The integrated circuit device of claim 9, wherein each of the read data, read request, write request, and write acknowledge signal types comprises a high-priority traffic type and a low-priority traffic type, and wherein each virtual channel comprises a respective sub-channel for each of the high-priority and low-priority traffic type of each signal type.

11. The integrated circuit device of claim 8, wherein the ring bus includes a virtual channel denoted a next ring stop channel for high priority traffic of each signal type, and wherein the next ring stop channel utilizes reserved buffer space within one or more ring bus components.

12. The integrated circuit device of claim 4, wherein the ring bus comprises two counter rotating transmission lines.

13. A memory controller coupling a plurality of memory clients on an integrated circuit device to external memory devices, comprising:

a plurality of read bus switches, each read bus switch of the plurality of read bus switches coupled to a respective memory device of the external memory devices;

one or more of the memory clients coupled to at least one read bus switch, and configured to transmit a memory request to a target memory device and receive a memory read transfer from the target memory device in response to the memory request, wherein each memory device represents a dynamic random access memory channel;

a central memory controller circuit coupled to at least one read bus switch and each of the one or more memory clients, and configured to route the memory request to the target memory device, wherein the memory controller circuit comprises,

a switch matrix configured to transmit the memory requests from the requesting memory client to the target memory device;

an arbiter circuit coupling each memory client of the one or more memory clients to a respective memory channel;

a sequencer circuit coupling each arbiter to a respective read bus switch corresponding to the requesting memory client; and

a client interface coupling the arbiter circuit to the requesting memory client and configured to implement a flow control protocol for the requesting memory client; and

a ring bus connected between pairs of read bus switches of the plurality of read bus switches, and configured to transmit the memory read transfer between the target memory device and a requesting memory client, wherein the ring bus comprises a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography.

14. The memory controller of 13, wherein each respective memory device comprises a dynamic random access memory.

15. An integrated circuit device including a memory control circuit, the integrated circuit device comprising:

a plurality of read bus switches, each read bus switch of the plurality of read bus switches coupled to a respective memory device located off of the integrated circuit device, wherein each memory device represents a dynamic random access memory channel;

one or more memory clients configured to transmit a memory request to a target memory device and receive a memory read transfer from the target memory device in response to the memory request, and coupled to each read bus switch of the plurality of read bus switches, wherein each read bus switch comprises,

a ring stop circuit configured to receive incoming read and write data traffic from adjacent ring stop circuits on the ring bus;

an arbiter circuit coupling the ring stop circuit to a respective memory channel;

a sequencer circuit coupling each arbiter to the respective memory channel; and

a client interface coupling the ring stop circuit to the requesting memory client; and

a ring bus connected between pairs of read bus switches of the plurality of read bus switches, the ring bus comprising a counter rotating ring bus coupling all of the plurality of read bus switches together in a ring topography, and configured to transmit both memory requests from a requesting client to a target memory device, and memory read transfers between the target memory device and the requesting memory client.

16. The integrated circuit device of claim 15, wherein read and write data traffic is organized using input and output queues in the ring stop circuit, and wherein input and output queues are prioritized depending in one of low priority and high priority data types.

17. The integrated circuit device of claim 16, wherein the arbiter circuit is configured to arbitrate data of the same priority using a round-robin algorithm.

18. A memory controller coupling a plurality of memory clients on an integrated circuit device to a plurality of memory devices, comprising:

a plurality of ring bus stops, each coupled to a respective memory device of the plurality of memory devices;

a memory controller circuit coupled to at least one ring bus stop and each of the plurality of memory clients, and configured to route memory access signals between the plurality of memory clients and memory devices;

a ring bus connected between pairs of ring bus stops, and configured to physically transmit the memory access signals between the plurality of memory clients and memory devices; and

a deadlock avoidance circuit comprising a next ring stop virtual channel for each ring bus stop and one or more reserved buffer entries in an input buffer of each ring bus stop, the deadlock avoidance circuit configured to prevent deadlock of the memory access signals on the ring bus, wherein the deadlock comprises multi-hop deadlock caused by filling an input buffer of a ring bus stop with transactions of any memory access signal type, and wherein the memory access signals comprise types consisting of;

read requests, write acknowledgments, read returns, and write requests.

19. The memory controller of claim 18, wherein the deadlock comprises read/write deadlock caused by two or more types of memory access signals sharing same physical channel of the ring bus.

20. The memory controller of claim 18, wherein the deadlock avoidance circuit comprises a virtual channel for each of the memory access signal types.

21. The memory controller of claim 20, wherein a subset of memory access signals are designated as next ring stop traffic, and wherein the next ring stop traffic is temporarily stored in the reserved buffer entries when the input buffer exceeds a predetermined storage level.