Method and apparatus for performing improved group instructions

• US 7,849,291 B2
• Filed: 10/29/2007
• Issued: 12/07/2010
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US11/842,038
• Publication Number:
  US 20090158012A1
• Time in Patent Office: 1,135 Days
• Field of Search: None
• US Class Current: 712/220
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: G06F 2212/2515 being configurable for different purposes, e.g. as cache or non-cache memory
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
• CPC Class Codes: H04N 21/2365 : Multiplexing of several video streams
• CPC Class Codes: H04N 21/238 : Interfacing the downstream path of the transmission network, e.g. adapting the transmission rate of a video stream to network bandwidth; Processing of multiplex streams hybrid fiber coaxial [HFC] networks for downstream channel allocation for video distribution H04L12/2801; flow control in packet networks H04L47/10; real-time communication protocols in data switching networks H04L65/00; scheduling or organising the servicing of application requests H04L67/60
• CPC Class Codes: H04N 21/23805 : Controlling the feeding rate to the network, e.g. by controlling the video pump
• CPC Class Codes: H04N 21/4347 : Demultiplexing of several video streams
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.

Claims

1. A programmable processor comprising:

an instruction path and a data path;

a register file comprising a plurality of registers coupled to the data path; and

an execution unit coupled to the instruction and data paths, that is operable to decode and execute group instructions received from the instruction path, and on an instruction-by-instruction basis, dynamically partition data from an operand register in the plurality of registers into multiple data elements having the same elemental width such that a total aggregate width of the multiple data elements equals a width of the operand register;

wherein the execution unit is capable of executing a first group operation that operates on data elements having a first elemental width and, immediately following execution of the first group operation, execute a second group operation that operates on data elements having a second elemental width twice as large as the first elemental width; and

wherein the execution unit is also capable of executing both group integer arithmetic operations and group floating-point arithmetic operations, wherein for the group integer arithmetic operations multiple pairs of integer data elements from a pair of operand registers are operated on in parallel to produce a catenated result comprising a plurality of individual integer results and for the group floating-point arithmetic operations multiple pairs of floating-point data elements from a pair of operand registers are arithmetically operated on in parallel to produce a catenated result comprising a plurality of individual floating-point results.

2. The programmable processor of claim 1 wherein the execution unit is capable of executing group integer and group floating-point instructions with precise exceptions available.

3. The programmable processor of claim 2 wherein, when a precise exception is generated during execution of a group floating-point instruction, the identity of the particular instruction causing the exception and its source operand values are available to be passed to software for handling.

4. The programmable processor of claim 1 wherein the execution unit is further capable of executing a plurality of different group floating-point arithmetic operations that each arithmetically operate in parallel on multiple sets of three floating-point data elements stored in three separate operand registers in the plurality of registers to produce a catenated result comprising a plurality of individual floating-point results that is returned to a register in the plurality of registers.

5. The programmable processor of claim 1 wherein the group floating-point arithmetic operations include group add, group subtract and group multiply arithmetic operations that operate on catenated floating-point data and the group integer arithmetic operations include group add, group subtract and group multiply arithmetic operations that operate on catenated integer data.

6. The programmable processor of claim 1 wherein the execution unit dynamically partitions data from an operand register in the plurality of registers according to a precision specified by a group instruction.

7. The programmable processor of claim 1 wherein a precision of a particular group integer arithmetic operation is specified by an opcode of the instruction that specifies the operation.

8. The programmable processor of claim 7 wherein a precision of a particular group floating-point arithmetic operation is specified by an opcode of the instruction that specifies the operation.

9. The programmable processor of claim 1 further comprising a virtual memory addressing unit that is part of a general purpose processor architecture capable of generating and handling virtual memory exceptions.

10. The programmable processor of claim 9 wherein the virtual memory addressing unit is capable of supporting a linear virtual address space, a segmented virtual address space and page mapping from virtual addresses to physical addresses.

11. The programmable processor of claim 1 further comprising an instruction pipeline that has a front stage and a back stage that is decoupled from the front stage by a memory buffer.

12. The programmable processor of claim 11 wherein the front stage handles address calculation, memory load and branch operations and the back stage handles data calculation and memory store operations.

13. The programmable processor of claim 1 further comprising an instruction pipeline having an address calculation stage, an execution stage and a memory buffer between the address calculation stage and execution stage to delay execution of instructions not ready.

14. The programmable processor of claim 1 wherein the execution unit comprises:

a first functional unit that performs arithmetic operations including group floating-point addition operations and group floating-point multiplication operations that each operate in parallel on multiple floating-point data elements stored in an operand register to produce a catenated result; and

a second functional unit that performs data handling operations including operations that copy, operations that shift, operations that rearrange and operations that resize multiple integer data elements stored in an operand register and produce a catenated result of the operation.

15. The programmable processor of claim 1 wherein the execution unit is further capable of executing a plurality of different group floating-point arithmetic operations that each arithmetically operate in parallel on multiple sets of three floating-point data elements stored in three separate operand registers in the plurality of registers to produce a catenated result comprising a plurality of individual floating-point results that is returned to a register in the plurality of registers.

16. The programmable processor of claim 1 wherein the catenated result is returned to a register in the plurality of registers.

17. The programmable processor of claim 1 wherein the floating-point data elements and the floating-point results have separate fields for a sign value, an exponent and a mantissa.

18. The programmable processor of claim 1 wherein the execution unit is also capable of performing group data handling operations including operations that copy, operations that shift, operations that rearrange and operations that resize multiple integer data elements from an operand register and produce a catenated result of the operation.

19. The programmable processor of claim 1 wherein the execution unit is capable of executing a group floating point operation that operates on multiple pairs of data elements having a first elemental width and, immediately following execution of the group floating point operation, execute a scalar floating-point operation that operates on a single pair of data elements having an elemental width twice as large as the first elemental width.

20. The programmable processor of claim 19 wherein the width of the data elements operated on by the scalar floating-point operation is equal to a width of a register in the register file.

21. A programmable processor comprising:

an instruction path and a data path;

a register file comprising a plurality of registers coupled to the data path; and

an execution unit coupled to the instruction and data paths, that is operable to decode and execute group instructions received from the instruction path and partition data from an operand register in the plurality of registers into multiple data elements having the same elemental width such that a total aggregate width of the multiple data elements equals a width of the operand register, wherein the execution unit can dynamically vary the elemental width of partitioned data based on information provided by an instruction being executed on an instruction-by-instruction basis, and wherein the execution unit is capable of, while operating in a single mode of operation;

(i) executing both group integer and group floating-point arithmetic operations in which multiple pairs of integer and floating-point data elements, respectively, from a pair of operand registers are operated on in parallel to produce a catenated result comprising a plurality of individual integer and floating-point results, respectively;

(ii) executing a first group operation that operates on data elements having a first elemental width and, immediately following execution of the first group operation, execute a second group operation that operates on data elements having a second elemental width twice as large as the first elemental width; and

(iii) executing a group floating point operation that operates on multiple pairs of data elements having the first elemental width and, immediately following execution of the group floating point operation, execute a scalar floating-point operation that operates on a single pair of data elements having the second elemental width.

22. The programmable processor of claim 21 wherein the execution unit is capable of executing group integer and group floating-point instructions with precise exceptions available.

23. The programmable processor of claim 22 wherein, when a precise exception is generated during execution of a group floating-point instruction, the identity of the particular instruction causing the exception and its source operand values are available to be passed to software for handling.

24. The programmable processor of claim 21 wherein the width of the data elements operated on by the scalar floating-point operation is equal to a width of a register in the register file.

25. A programmable processor comprising:

an instruction path and a data path;

a register file comprising a plurality of registers coupled to the data path; and

an execution unit coupled to the instruction and data paths, that is operable to decode and execute group instructions received from the instruction path and partition data from an operand register in the plurality of registers into multiple data elements having the same elemental width such that a total aggregate width of the multiple data elements equals a width of the operand register, wherein the execution unit can dynamically vary the elemental width and data type of partitioned data on an instruction-by-instruction basis and is capable of;

(i) executing both group integer and group floating-point arithmetic operations in which multiple pairs of integer and floating-point data elements, respectively, from a pair of operand registers are operated on in parallel to produce a catenated result comprising a plurality of individual integer and floating-point results, respectively;

(ii) executing a first group operation that operates on data elements having a first elemental width and, immediately following execution of the first group operation, execute a second group operation that operates on data elements having a second elemental width twice as large as the first elemental width;

(iii) executing a group floating point operation that operates on multiple pairs of data elements having the first elemental width and, immediately following execution of the group floating point operation, execute a scalar floating-point operation that operates on a single pair of data elements having the second elemental width; and

(iv) executing group integer and group floating-point instructions while making available precise exceptions.

26. The programmable processor of claim 25 wherein, when a precise exception is generated during execution of a group floating-point instruction, the identity of the particular instruction causing the exception and its source operand values are available to be passed to software for handling.