Method of fabricating a trench gate MOSFET for maximizing breakdown voltage

• US 7,851,300 B2
• Filed: 12/28/2008
• Issued: 12/14/2010
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: DB HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd. (DB HiTek Co., Ltd.)
• Inventors: Kim, Hee-Dae
• Primary Examiner(s): Dickey; Thomas L
• Application Number:
  US12/344,563
• Publication Number:
  US 20090166734A1
• Time in Patent Office: 716 Days
• Field of Search: 357/330, 357/331, 257/330, 257/331, 438/243, 438/272
• US Class Current: 438/243
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A trench gate MOSFET and a fabrication method thereof includes forming a first epitaxial layer over a semiconductor substrate, and then forming a second epitaxial layer formed over the first epitaxial layer, and then forming a body region over the second conductive type second epitaxial layer, and then forming a circular cross-section in a portion of the body region by performing an ion implantation process on the body region such that a bottom area thereof has a circular cross-section.

Claims

1. A method comprising:

forming a second conductive type first epitaxial layer and a second conductive type second epitaxial layer over a first conductive type semiconductor substrate; and

then

forming a first conductive type body region over the second conductive type second epitaxial layer; and

then

injecting first conductive type impurities in the first conductive type body region in order that a bottom area thereof has a circular cross-section; and

then

forming a plurality of trenches spaced apart in the first conductive body region; and

then

forming a gate oxide layer in a respective one of the trenches; and

then

forming a gate in a respective one of the trenches; and

then

forming second conductive type emitter regions in the first conductive type body region; and

then

forming a contact hole at the upper surface of the first conductive type body region between adjacent ones of the second conductive type emitter regions,

wherein the first conductive type body region between the bottom area of the contact hole and the second conductive type second epitaxial layer is formed to maintain a predetermined thickness.

2. The method of claim 1, further comprising, after forming the plurality of trenches and before forming the gate:

etching the walls the trenches.

3. The method of claim 1, further comprising, after etching the walls of the trenches:

forming a sacrificial oxide layer over the walls of the trench.

4. The method of claim 1, wherein the bottom area of the first conductive type body region corresponds spatially to the bottom area of the contact hole.