Routingless chip architecture

• US 7,851,348 B2
• Filed: 01/10/2006
• Issued: 12/14/2010
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John, Misra, Abhay
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US11/329,540
• Publication Number:
  US 20060281296A1
• Time in Patent Office: 1,799 Days
• Field of Search: 438/618, 438/107, 438/597, 438/637, 438/667, 438/625
• US Class Current: 438/618
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/06596 : Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of creating a unified chip involves performing front-end processing on a first wafer, the front end processing creating multiple devices on the wafer, performing back-end processing on a second wafer, the back end processing creating layers of interconnected metal traces arranged to interconnect at least some of the multiple devices to each other, and bonding the first wafer to the second wafer such that the multiple devices on the first wafer are interconnected to each other by the metal traces of the second wafer.

Claims

1. A method for creating a unified chip, comprising:

performing a front-end process on a first wafer, wherein the front-end process creates multiple devices on the first wafer, and wherein at least some of the multiple devices have electrical connection points;

performing a back-end process on a second wafer, wherein the back-end process creates layers of metal traces arranged to interconnect at least some of the multiple devices; and

bonding the first wafer to the second wafer so that the at least some of the multiple devices on the first wafer are interconnected by the metal traces of the second wafer.

2. The method of claim 1, further comprising thinning a substrate of the first wafer prior to bonding the first wafer to the second wafer.

3. The method of claim 1, further comprising thinning a substrate of the second wafer prior to bonding the first wafer to the second wafer.

4. The method of claim 1, further comprising thinning a substrate side of the second wafer until the metal traces are exposed on the substrate side, wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that at least some of the multiple devices on the first wafer are interconnected by the metal traces on the substrate side of the second wafer.

5. The method of claim 4, further comprising attaching devices of another chip to the metal traces on a side opposite the substrate side of the second wafer.

6. The method of claim 1, further comprising thinning a substrate side of the first wafer until at least some of the electrical connection points are exposed on the substrate side, wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that the metal traces of the second wafer are bonded to the electrical connection points exposed on the substrate side of the first wafer.

7. The method of claim 1, further comprising, prior to bonding the first wafer to the second wafer:

thinning a substrate side of the first wafer until at least some of the electrical connection points are exposed on the substrate side of the first wafer; and

thinning a substrate side of the second wafer until the metal traces are exposed on the substrate side of the second wafer;

wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that the metal traces on the substrate side of the second wafer are bonded to at least some of the electrical connection points exposed on the substrate side of the first wafer.

8. The method of claim 1, wherein said performing a front-end process on the first wafer and said performing a back-end process on the second wafer at least partially overlap in time.

9. The method of claim 1, wherein said performing a front-end process on a first wafer and said performing a back-end process on a second wafer occur substantially concurrently.

20. The method of claim 1, further comprising:

forming a first via into the first wafer such that the first via is electrically connected to a first device of the multiple devices; and

forming a second via into the second wafer such that the second via is electrically connected to at least one of the layers of metal traces;

wherein said bonding the first wafer to the second wafer comprises electrically connecting the first via to the second via.

21. The method of claim 20, wherein said forming a second via comprises forming the second via only part-way through the second wafer such that the second via is electrically connected to a particular layer of metal traces disposed within the second wafer.

22. The method of claim 20, wherein the second via is a through-wafer via that extends entirely through the second wafer.

23. The method of claim 1, wherein at least some of the layers of metal traces comprise a plurality of vertically-stacked layers.

24. The method of claim 23, wherein at least some of the layers of metal traces extend substantially across a length of the second wafer.

10. A method for creating a unified chip, comprising:

providing a first wafer having multiple devices created in a front-end process, wherein at least some of the multiple devices have electrical connection points;

providing a second wafer having layers of metal traces created in a back-end process and arranged to interconnect at least some of the multiple devices; and

bonding the first wafer to the second wafer so that the at least some of the multiple devices on the first wafer are interconnected by the metal traces of the second wafer.

11. The method of claim 10, wherein said bonding the first wafer to the second wafer comprises at least one of:

performing a wafer fusion process;

bringing the first and second wafers together such that van der Waals forces attach the first wafer to the second wafer;

bringing the first and second wafers together such that covalent bonding occurs between the first and second wafers;

performing a tack process;

or

performing a fuse process.

12. The method of claim 10, further comprising thinning a substrate of the first wafer prior to bonding the first wafer to the second wafer.

13. The method of claim 10, further comprising thinning a substrate of the second wafer prior to bonding the first wafer to the second wafer.

14. The method of claim 10, further comprising thinning a substrate side of the second wafer until the metal traces are exposed on the substrate side, wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that at least some of the multiple devices on the first wafer are interconnected by the metal traces on the substrate side of the second wafer.

15. The method of claim 14, further comprising attaching devices of another chip to the metal traces on a side opposite the substrate side of the second wafer.

16. The method of claim 10, further comprising thinning a substrate side of the first wafer until at least some of the electrical connection points are exposed on the substrate side, wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that the metal traces of the second wafer are bonded to the electrical connection points exposed on the substrate side of the first wafer.

17. The method of claim 10, further comprising, prior to bonding the first wafer to the second wafer:

thinning a substrate side of the first wafer until at least some of the-electrical connection points are exposed on the substrate side of the first wafer; and

thinning a substrate side of the second wafer until the metal traces are exposed on the substrate side of the second wafer;

wherein said bonding the first wafer to the second wafer comprises bonding the first wafer to the second wafer so that the metal traces on the substrate side of the second wafer are bonded to at least some of the electrical connection points exposed on the substrate side of the first wafer.

18. The method of claim 10, wherein the front-end process on the first wafer is performed over a first time period and the back-end process on the second wafer is performed over a second time period that at least partially overlaps the first time period.

19. The method of claim 10, wherein the front-end process on the first wafer and the back-end process on the second wafer are performed concurrently.