Integrated circuit and methods of manufacturing the same

• US 7,851,356 B2
• Filed: 09/28/2007
• Issued: 12/14/2010
• Est. Priority Date: 09/28/2007
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Muemmler, Klaus, Mierau, Uta, Tegen, Stefan, Baars, Peter
• Primary Examiner(s): Sarkar; Asok K
• Assistant Examiner(s): Slutsker; Julia
• Application Number:
  US11/863,528
• Publication Number:
  US 20090085084A1
• Time in Patent Office: 1,173 Days
• Field of Search: 438/637, 438/672, 438/618, 257/E21.678
• US Class Current: 438/637
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A method of manufacturing an integrated circuit includes forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region. The method also includes forming wiring lines within a peripheral region of the substrate. Forming the landing pads and forming the wiring lines includes a common lithographic process being effective in both the array and peripheral regions. The wiring lines and the landing pads of the integrated circuit are self-aligned.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming landing pads in an array region of a substrate, individual ones of the landing pads being electrically coupled to individual ones of portions of devices formed in the substrate in the array region; and

forming wiring lines within a peripheral region of the substrate;

wherein forming the landing pads and forming the wiring lines comprises a common lithographic process being effective both in the array and peripheral regions and comprising;

a first lithographic exposure process using a first mask comprising first line structures in an array portion corresponding to the array region and wiring line structures in a peripheral portion corresponding to the peripheral region; and

a second lithographic exposure process using a second mask with second line structures in the array portion corresponding to the array region and with a block structure in the peripheral portion corresponding to the peripheral region, the second line structures intersecting the first line structures,

wherein intersecting portions of the first and the second line structures correspond to the landing pads.

2. The method of claim 1, further comprising:

forming contact plugs in the array region before forming the landing pads, lower surfaces of the individual ones of the contact plugs being in contact with individual ones of the portions of the devices and upper surfaces of the individual ones of the contact plugs being in contact with individual ones of the landing pads.

3. The method of claim 1, wherein forming the landing pads and forming the wiring lines further comprises:

patterning a layer of a conductive material disposed in the peripheral region and in the array region such that the conductive material is electrically coupled to the portions of the devices.

4. The method of claim 1, further comprising:

providing a conductive layer above the peripheral region and the array region before carrying out the common lithographic process, the conductive layer being electrically coupled to the portions of the devices;

providing a masking layer above the conductive layer and patterning the masking layer by carrying out the common lithographic process to form landing pad structures within the masking layer in the array region and wiring line structures within the masking layer in the peripheral region; and

patterning the conductive layer using the patterned masking layer as an etching mask.

5. The method of claim 4, further comprising:

forming contact portions comprising a semiconductor material, the contact portions being exposed at a top surface of the array region and electrically coupling the conductive layer to the portions of the devices; and

forming a metal-semiconductor compound before providing the conductive layer.

6. The method of claim 1, further comprising:

providing a masking layer above the peripheral region and the array region before carrying out the common lithographic process;

patterning the masking layer by carrying out the common lithographic process, thereby forming structures in the masking layer, the structures being holes having the shape of the landing pads in the array region and being trenches having the shape of the wiring lines in the peripheral region; and

at least partially filling the structures in the masking layer with a conductive material.

7. The method of claim 6, further comprising:

forming contact portions in the array region, the contact portions being electrically coupled to the portions of the devices;

wherein the structures in the array region extend to an upper surface of the contact portions.

8. The method of claim 7, further comprising:

forming a metal-semiconductor compound in the structures above the contact portions before filling the structures with the conductive material;

wherein the contact portions comprise a semiconductor material.

9. The method of claim 1, wherein the first and second lithographic exposure processes are effective on one resist layer system.

10. The method of claim 1, wherein the first lithographic exposure process is effective on a first resist layer system and the second lithographic process is effective on a second resist layer system.

11. The method of claim 1, wherein the devices formed in the array region are access transistors of memory cells and the portions of the devices are source/drain regions of the transistors, the method further comprising:

forming first and second conductive lines in the array region, individual ones of the access transistors being configured to be addressed by at least one first and one second conductive line; and

forming storage capacitors above the access transistors in the array region, individual ones of the storage capacitors being electrically coupled to individual ones of the landing pads.