Method of forming a low capacitance semiconductor device and structure therefor

• US 7,851,852 B2
• Filed: 10/07/2009
• Issued: 12/14/2010
• Est. Priority Date: 09/16/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Venkatraman, Prasad
• Primary Examiner(s): Tran; Long K
• Application Number:
  US12/574,934
• Publication Number:
  US 20100025745A1
• Time in Patent Office: 433 Days
• Field of Search: 257/315, 257/327, 257/341, 257/390, 257/401, 257/620, 257/E29.027, 257/E29.121, 257/E29.257
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment a transistor is formed with a gate structure having an opening in the gate structure. An insulator is formed on at least sidewalls of the opening and a conductor is formed on the insulator.

Claims

1. A semiconductor device comprising:

a substrate of a first conductivity type having a first surface;

a first source region of the first conductivity type on the first surface of the substrate;

a second source region of the first conductivity type on the first surface of the substrate wherein the second source region is spaced apart from the first source region;

a gate structure overlying the first surface of the substrate, the gate structure having a first end overlying an edge of the first source region, a second end overlying an edge of the second source region, the gate structure having a first surface substantially parallel to the first surface of the substrate and facing away from the first surface of the substrate;

a gate conductor of the gate structure overlying the substrate;

an insulator layer of the gate structure on the gate conductor;

a first conductor on the insulator layer; and

a source conductor formed on the first conductor subsequently to forming the first conductor.

2. The semiconductor device of claim 1 wherein the insulator layer is no thicker than about 10,000 Angstroms.

3. The semiconductor device of claim 1 wherein the first conductor includes doped polysilicon.

4. The semiconductor device of claim 1 wherein the first surface of the gate structure is devoid of an opening extending into the gate structure.