MOSFET device including a source with alternating P-type and N-type regions

• US 7,851,889 B2
• Filed: 04/30/2007
• Issued: 12/14/2010
• Est. Priority Date: 04/30/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Zhu, Ronghua, Bose, Amitava, Khemka, Vishnu K., Roggenbauer, Todd C.
• Primary Examiner(s): Smith; Matthew S
• Assistant Examiner(s): Jefferson; Quovaunda
• Application Number:
  US11/742,363
• Publication Number:
  US 20080265291A1
• Time in Patent Office: 1,324 Days
• Field of Search: 257/331, 257/341, 257/401, 257/E29.257, 257/E23.079, 257/E21.418, 257/547, 257/548, 257/550, 257/E29.021, 257/E29.039, 257/E29.04, 257/E29.12
• US Class Current: 257/547
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the surface, and the transistor source includes an area (310) of alternating conductivity regions (3110, 3120). Another apparatus includes a semiconductor body (120) including a first conductivity and a transistor source (500) located in the semiconductor body. The transistor source includes multiple regions (5120) including a second conductivity, wherein the regions and the semiconductor body form an area (510) of alternating regions of the first and second conductivities. One method includes implanting a semiconductor well (120) including a first conductivity in a substrate (110) and implanting a plurality of doped regions (5120) comprising a second conductivity in the semiconductor well. An area (510) comprising regions of alternating conductivities is then formed in the semiconductor well.

Claims

1. A semiconductor device, comprising:

a semiconductor body comprising a surface;

a transistor drain located in the semiconductor body proximate the surface;

a transistor source located in the semiconductor body proximate the surface and spaced apart from the transistor drain, wherein a direction of current flow extends between the transistor drain and the transistor source; and

a first area comprising multiple p-type regions and multiple n-type regions that are interdigitated with each other in an alternating arrangement and are located in the transistor source at the surface, wherein the p-type regions and n-type regions are interdigitated along a first direction that is perpendicular to the direction of current flow, and the p-type regions and n-type regions have lengths and abutting edges that are parallel with the surface and extend along a second direction that is parallel to the direction of current flow.

2. The semiconductor device of claim 1, the source further comprising a silicide layer covering at least a portion of the first area.

3. The semiconductor device of claim 1, further comprising a second area comprising alternating p-type regions and n-type regions located in the transistor source.

4. The semiconductor device of claim 3, the source further comprising one of a p-type region and an n-type region separating the first area and the second area.

5. The semiconductor of claim 4, further comprising a first polysilicon region adjacent the first area.

6. The semiconductor of claim 5, further comprising a second polysilicon region adjacent the second area.

7. The semiconductor device of claim 4, further comprising at least one source contact located within the one of the p-type region and the n-type region separating the first area and the second area.

8. The semiconductor device of claim 7, wherein the at least one source contact comprises a plurality of source contacts within the one of the p-type region and the n-type region separating the first area and the second area.

9. The semiconductor device of claim 1, further comprising:

a first polysilicon region located in the transistor source; and

a second polysilicon region located in the transistor source, the first area separating the first and second polysilicon regions.

10. The semiconductor device of claim 1, wherein the p-type regions and the n-type regions are aligned parallel to one another and interdigitated along a device width direction, while current flow is along a device length direction.

11. The semiconductor device of claim 1, wherein the p-type regions and the n-type regions each have a junction depth in a range of about 0.05 μ

m to about 0.5 μ

m.

12. The semiconductor device of claim 1, further comprising a source well formed in the semiconductor body, wherein the p-type regions and the n-type regions are located in the source well.

13. The semiconductor device of claim 1, further comprising at least one source contact located within the first area.

14. The semiconductor device of claim 13, wherein the at least one source contact comprises a plurality of source contacts within a plurality of the p-type regions and the n-type regions.

15. A semiconductor device, comprising:

a semiconductor body comprising a surface;

a transistor source located in the semiconductor body proximate the surface; and

a first area comprising alternating p-type regions and n-type regions located in the transistor source, wherein the first area comprises a silicided block region separating a p-type region from an n-type region.

16. A semiconductor device, comprising:

a semiconductor body comprising a surface and a first conductivity type;

a transistor drain located in the semiconductor body proximate the surface;

a transistor source located in the semiconductor body proximate the surface and spaced apart from the transistor drain, wherein a direction of current flow extends between the transistor drain and the transistor source; and

a first plurality of regions comprising a second conductivity type located in the transistor source at the surface, the first plurality of regions and the semiconductor body forming a first area of alternating regions of the first and second conductivity types, wherein the alternating regions are interdigitated along a first direction that is perpendicular to the direction of current flow, and the alternating regions have lengths and abutting edges that are parallel with the surface and extend along a second direction that is parallel to the direction of current flow.

17. The semiconductor device of claim 16, further comprising a second plurality of regions comprising the second conductivity type located in the semiconductor body, the second plurality of regions and the semiconductor body forming a second area of alternating regions of the first and second conductivity types.

18. The semiconductor device of claim 17, further comprising a doped region comprising one of the first conductivity type and the second conductivity type separating the first and second areas.

19. The semiconductor device of claim 16, wherein the first conductivity type is an n-type conductivity and the second conductivity type is a p-type conductivity.

20. The semiconductor device of claim 16, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.