Multichip package or system-in package

• US 7,851,898 B2
• Filed: 03/21/2006
• Issued: 12/14/2010
• Est. Priority Date: 03/22/2005
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd., Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Hirose, Yukitoshi, Katagiri, Mitsuaki, Nakamura, Satoshi, Suga, Takashi
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Chiu; Tsz K
• Application Number:
  US11/384,277
• Publication Number:
  US 20060227587A1
• Time in Patent Office: 1,729 Days
• Field of Search: 257/686, 257/777, 257/685, 257/690, 257/723, 257/773, 257/E21.526, 257/E23.171, 257/E25.013
• US Class Current: 257/685
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/06568 the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

Disclosed is a multichip package or system-in package which the logic chip includes a selector circuit which, by transmitting a test mode select signal or a test mode select command to the logic chip, enables access from a logic signal pin connected to the logic chip, to a memory control signal to each of the “m” number of memory chips; and the memory control signal, when viewed from the logic chip, is connected using a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme, between the selector circuit and each of the “m” number of memory chips. This multichip package or system-in package is low in noise and high in operational reliability.

Claims

1. A semiconductor package constructed by mounting, on a front surface of a package substrate, at least one memory chip and a logic chip for controlling the at least one memory chip, wherein:

the package substrate has four layers and a rear surface,

a first pin is provided on the rear surface of the package substrate and electrically connected to the logic chip,

a second pin is provided on the rear surface of the package substrate for transmitting a test signal and transmitting a logic signal,

the logic chip includes a selector circuit which is configured to switch, in response to a test mode select signal, a signal path from a normal operation mode to a test mode which enables access from the second pin to a memory control signal to the at least one memory chip,

the second pin transmits the test signal when the selector is in a test mode and transmits the logic signal when the selector circuit is in a normal operation mode, and

power supply wiring for the logic chip and power supply wiring for the at least one memory chip are allocated to either the third layer of the package substrate or the third layer and next lower layer of the package substrate in the package substrate including at least four wiring layers, said allocated power supply wiring for the logic chip supplying electric power thereto by being connected from a power supply pin for the logic chip to thereto via the allocated power supply wiring for the logic chip, said allocated power supply wiring for the at least one memory chip supplying electric power to each thereof by being connected from power supply pins for the at least one memory chip to each thereof via the allocated power supply wiring for the at least one memory chip.

2. The semiconductor package according to claim 1, wherein

the memory control signal connection uses a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme which includes:

a wire-bonding connection or bump connection established via wiring formed on a first layer, or on the first layer and a second layer of the package substrate including at least four wiring layers;

or

a direct wire-bonding connection or bump connection established between the logic chip the at least one memory chip.

3. The semiconductor package according to claim 2, wherein test-only pins, which are to directly access the at least one memory chip, are removed from the package substrate.

4. The semiconductor package according to claim 1, the memory control signal connection uses a one-for-one wiring scheme or a one-for-up-to-m branch wiring scheme which includes:

a wire-bonding connection or bump connection established via wiring formed on a signal wiring layer, or on the signal wiring layer and a GND wiring layer of the package substrate having at least four wiring layers;

or

a direct wire-bonding connection or bump connection established between the logic chip the at least one memory chip.

5. The semiconductor package according to claim 4, wherein test-only pins, which are to directly access the at least one memory chip, are removed from the package substrate.

6. The semiconductor package according to claim 1, wherein a total area of the allocated power supply wiring for the logic chip and the allocated power supply wiring for the at least one memory chip is at least 40% of an area of the package substrate.

7. The semiconductor package according to claim 1, wherein a total area of the allocated power supply wiring for the logic chip and the allocated power supply wiring for the at least one memory chip is at least 40% of a GND wiring area of the package substrate.