Class-D amplifier and method therefor

• US 7,852,155 B2
• Filed: 03/03/2006
• Issued: 12/14/2010
• Est. Priority Date: 03/03/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Chaoui, Hassan
• Primary Examiner(s): Mottola; Steven J
• Application Number:
  US11/572,431
• Publication Number:
  US 20090184765A1
• Time in Patent Office: 1,747 Days
• Field of Search: 330/10, 330/207.A, 330/251
• US Class Current: 330/251
• CPC Class Codes: H03F 1/52 Circuit arrangements for protecting such amplifiers monitoring arrangements G01R31/28; increasing reliability in communication systems, e.g. using redundancy H04B1/74
• CPC Class Codes: H03F 2200/114 the amplifier comprising means for electro-magnetic interference [EMI] protection
• CPC Class Codes: H03F 2203/7221 the gated amplifier being switched on or off by a switch at the output of the amplifier
• CPC Class Codes: H03F 2203/7239 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers and shunting lines by one or more switch(es)
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03F 3/2178 using more than one switch or switching amplifier in parallel or in series H03F3/2173, H03F3/2175 take precedence
• CPC Class Codes: H03F 3/423 with MOSFET's
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

In one embodiment, a class-D amplifier (11) is configured to form first (DP) and second (DN) PWM signals each having a duty cycle that is proportional to a received analog input signal (12) and responsively to enable a switch (31, 32) to short the outputs (13, 14) of the class-D amplifier (11) together responsively to some states of the first (DP) and second (DN) PWM signals.

Claims

1. A class-D amplifier comprising:

a first switch and a second switch coupled as a first pair of stacked switches having a first output at a common node between the first switch and the second switch;

a third switch and a fourth switch coupled as a second pair of stacked switches having a second output at a common node between the third switch and the fourth switch; and

a control circuit operably coupled to short only the first output to the second output, the control circuit including a fifth switch coupled between the first output of the first pair of stacked switches and the second output of the second pair of stacked switches wherein the control circuit is configured to operate the fifth switch to short the first output to the second output, the control circuit configured to receive an input signal and responsively form a first pulse width modulated signal having a first duty cycle that is determined by an amplitude of the input signal and also responsively form a second pulse width modulated signal having a second duty cycle that is determined by an amplitude of the input signal wherein a difference between the first duty cycle and the second duty cycle is proportional to an amplitude of the input signal.

2. The class-D amplifier of claim 1 further including the control circuit configured to use the first pulse width modulated signal and the second pulse width modulated signal to inhibit the class-D amplifier from supplying current to the output of the class-D amplifier.

3. The class-D amplifier of claim 1 wherein the class-D amplifier is configured to supply current to the output of the class-D amplifier responsively to a difference between the first duty cycle and the second duty cycle.

4. The class-D amplifier of claim 1 wherein the first pulse width modulated signal and the second pulse width modulated signal have a fixed frequency.

5. A class-D amplifier comprising:

a first switch and a second switch coupled as a first pair of stacked switches having a first output at a common node between the first switch and the second switch;

a third switch and a fourth switch coupled as a second pair of stacked switches having a second output at a common node between the third switch and the fourth switch;

a control circuit operably coupled to short only the first output to the second output, the control circuit including a fifth switch coupled between the first output of the first pair of stacked switches and the second output of the second pair of stacked switches wherein the control circuit is configured to operate the fifth switch to short the first output to the second output; and

a sixth switch coupled between the first output of the first pair of stacked switches and the second output of the second pair of stacked switches wherein the control circuit is configured to operate the sixth switch to short the first output to the second output.

6. A class-D amplifier comprising:

a first switch and a second switch coupled as a first pair of stacked switches having a first output at a common node between the first switch and the second switch;

a third switch and a fourth switch coupled as a second pair of stacked switches having a second output at a common node between the third switch and the fourth switch; and

a control circuit operably coupled to short only the first output to the second output, the control circuit including a fifth switch coupled between the first output of the first pair of stacked switches and the second output of the second pair of stacked switches wherein the control circuit is configured to operate the fifth switch to short the first output to the second output, the control circuit operably coupled to hold a voltage on outputs of the class-D amplifier to a value that is approximately at a mid-point between a value of a voltage return of the class-D amplifier and a value of an operating voltage of the class-D amplifier.

7. The class-D amplifier of claim 6 wherein the control circuit is operably coupled to disable the first pair of stacked switches and the second pair of stacked switches to inhibit the class-D amplifier from supplying current to the outputs of the class-D amplifier.

8. A method of forming a class-D amplifier comprising:

operably coupling the class-D amplifier to form digital signals responsively to an analog input signal;

configuring the class-D amplifier to supply current to outputs of the class-D amplifier responsively to the digital signals; and

configuring a control circuit of the class-D amplifier to inhibit the class-D amplifier from supplying current to the outputs responsively to a state of the digital signals representing a non-zero value of the analog input signal and hold a voltage on the outputs of the class-D amplifier to a voltage that is approximately at a mid-point between a voltage return of the class-D amplifier and an operating voltage of the class-D amplifier.

9. The method of claim 8 wherein operably coupling the class-D amplifier to form digital signals responsively to the analog input signal includes configuring the class-D amplifier to form a first PWM signal having a first duty cycle that is derived from an amplitude of the analog input signal and a second PWM signal having a second duty cycle that is derived from the amplitude of the analog input signal wherein a difference between the first duty cycle and the second duty cycle is proportional to the amplitude of the analog input signal.

10. The method of claim 9 wherein configuring the control circuit of the class-D amplifier to inhibit the class-D amplifier from supplying current to the outputs responsively to the state of the digital signals includes configuring the control circuit of the class-D amplifier to inhibit the class-D amplifier from supplying current to the outputs responsively to the first PWM signal and the second PWM signal.

11. The method of claim 8 wherein configuring the control circuit of the class-D amplifier to inhibit the class-D amplifier from supplying current to the outputs includes configuring the control circuit to couple the outputs together.

12. The method of claim 11 wherein configuring the control circuit to couple the outputs together includes configuring the control circuit to couple the outputs together when the digital signals are in a common state.

13. The method of claim 8 wherein configuring the control circuit of the class-D amplifier to inhibit the class-D amplifier from supplying current to the outputs includes operably coupling the control circuit to inhibit supplying current to the outputs when the digital signals are in a common state.

14. A class-D amplifier comprising:

a first circuit operably coupled to receive an analog signal and responsively form digital signals representative of the analog signal;

an H-bridge circuit having first and second outputs, the H-bridge circuit operably coupled to supply current to the outputs and sink current from the outputs responsively to the digital signals;

a first switch coupled in parallel between the first and second outputs of the H-bridge circuit; and

a second switch coupled in parallel with the first switch.

15. The class-D amplifier of claim 14 further including control logic configured to form first and second control signals from the digital signals wherein the first control signal enables the first switch for common states of the digital signals and the second control signal enables the second switch for common states of the digital signals.

16. The class-D amplifier of claim 14 wherein the first switch is operability coupled to inhibit the class-D amplifier from supplying current to the outputs responsively to the digital signals.

17. The class-D amplifier of claim 14 further including control logic configured to form a control signal from the digital signals wherein the control signal enables the first switch for common states of the digital signals.