Spin-torque MRAM: spin-RAM, array
First Claim
1. A spin-torque MRAM cell array comprising:
- a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising;
a magnetic tunnel junction element, anda select switching device having a drain terminal connected to a first terminal of said magnetic tunnel junction element;
a plurality of bit lines, each bit line associated with one column of the columns of the plurality of spin-torque MRAM cells and connected to a second terminal of said magnetic tunnel junction element;
a plurality of word lines, each word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of said select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of said select switching device;
a plurality of source select lines, each source select line placed orthogonally to said plurality of bit lines and associated with one pair of rows of said plurality of spin-torque MRAM cells and connected to a source terminal of said select switching device of each of said spin-torque MRAM cells on the associated pair of rows of said plurality of spin-torque MRAM cells wherein each source select line transmits a source line input signal applied to the source of the select switching device of at least one of the plurality of spin-torque MRAM cells on a selected word line and is set at a first logic level during a first writing step of selected spin-torque MRAM cells on the selected word line and subsequently toggled to a second logic level during a second writing step, wherein the first logic level is different from the second logic level; and
a plurality of column write select devices, each column write select device associated with one column of said plurality of spin-torque MRAM cells and having a source terminal connected to the associated bit line of said plurality of bit lines, a drain terminal connected to receive a data input signal and a gate terminal connected to receive one of a plurality of column write select signals.
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Accused Products
Abstract
A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.
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Citations
35 Claims
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1. A spin-torque MRAM cell array comprising:
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a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising; a magnetic tunnel junction element, and a select switching device having a drain terminal connected to a first terminal of said magnetic tunnel junction element; a plurality of bit lines, each bit line associated with one column of the columns of the plurality of spin-torque MRAM cells and connected to a second terminal of said magnetic tunnel junction element; a plurality of word lines, each word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of said select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of said select switching device; a plurality of source select lines, each source select line placed orthogonally to said plurality of bit lines and associated with one pair of rows of said plurality of spin-torque MRAM cells and connected to a source terminal of said select switching device of each of said spin-torque MRAM cells on the associated pair of rows of said plurality of spin-torque MRAM cells wherein each source select line transmits a source line input signal applied to the source of the select switching device of at least one of the plurality of spin-torque MRAM cells on a selected word line and is set at a first logic level during a first writing step of selected spin-torque MRAM cells on the selected word line and subsequently toggled to a second logic level during a second writing step, wherein the first logic level is different from the second logic level; and a plurality of column write select devices, each column write select device associated with one column of said plurality of spin-torque MRAM cells and having a source terminal connected to the associated bit line of said plurality of bit lines, a drain terminal connected to receive a data input signal and a gate terminal connected to receive one of a plurality of column write select signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A spin-torque magnetic random access memory device comprising
a plurality of spin-torque MRAM cell arrays arranged in a plurality of groups, each spin-torque MRAM array comprising: -
a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising; a magnetic tunnel junction element, and a select switching device having a drain terminal connected to a first terminal of said magnetic tunnel junction element; a plurality of bit lines, each bit line associated with one column of the columns of the plurality of spin-torque MRAM cells and connected to a second terminal of said magnetic tunnel junction element, a plurality of word lines, each word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of said select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of said select switching device, a plurality of source select lines, each source select line placed orthogonally to said plurality of bit lines and associated with one pair of rows of said plurality of spin-torque MRAM cells and connected to a source terminal of said select switching device of each of said spin-torque MRAM cells on the associated pair of rows of said plurality of spin-torque MRAM cells wherein each source select line transmits a source line input signal applied to the source of the select switching device of at least one of the plurality of spin-torque MRAM cells on a selected word line and is set at a first logic level during a first writing step of selected spin-torque MRAM cells on the selected word line and subsequently toggled to a second logic level during a second writing step, wherein the first logic level is different from the second logic level, and a plurality of column write select devices, each column write select device associated with one column of said plurality of spin-torque MRAM cells and having a source terminal connected to the associated bit line of said plurality of bit lines, a drain terminal connected to receive a data input signal and a gate terminal connected to receive one of a plurality of column write select signals; a bit line decode circuit to receive an address, input data, and a read/write select signal, decode said address, input data, and read/write select signal, and in communication with said plurality of bit lines, said drain terminals, and gate terminals of each of said plurality of write select devices to select which of said bit lines are activated for reading one of said spin-torque MRAM cells on each selected column and activate those of said column write select devices of a selected column to transfer said input data signal derived from said input data to one selected spin-torque MRAM cell on at least one said selected column; a word line decode circuit to receive said address and in communication with each of said plurality of word lines, and decoding said address to activate one of said word lines on one row of said array of spin-torque MRAM cells; and a select line decode circuit to receive said address and said read/write select signal to decode said address and in communication with each of said plurality of source select lines to select one of said source select lines from decoding said address to provide the first logic level and the second logic level for reading and said source line input signal for writing said selected spin-torque MRAM cells. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A method for programming a spin-torque MRAM cell array comprising the steps of:
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providing a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising; a magnetic tunnel junction element, and a select switching device having a drain terminal connected to a first terminal of said magnetic tunnel junction element; providing a plurality of bit lines by the step of; associating each bit line with one column of the columns of the plurality of spin-torque MRAM cells and connecting each bit line to a second terminal of said magnetic tunnel junction element; providing a plurality of word lines by the step of; associating each word line with one row of the plurality of spin-torque MRAM cells and connecting each word line to a gate terminal of said select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of said select switching device; providing a plurality of source select lines by the step of; placing each source select line orthogonally to said plurality of bit lines, and associating each source select line with one pair of rows of said plurality of spin-torque MRAM cells and connecting each source select line to a source terminal of said select switching device of each of said spin-torque MRAM cells on the associated pair of rows of said plurality of spin-torque MRAM cells, and transmitting on each source select line a source line input signal that is applied to the source of the select switching device of at least one of the plurality of spin-torque MRAM cells on a selected word line, setting the source line input signal to a first logic level during a first writing step of selected spin-torque MRAM cells on the selected word line, subsequently toggling the source line input signal to a second logic level during a second writing step, wherein the first logic level is different from the second logic level; and providing a plurality of column write select devices by the step of; associating each column write select device associated with one column of said plurality of spin-torque MRAM cells and having a source terminal connected to each of said plurality of bit lines, a drain terminal connected to receive a data input signal and a gate terminal connected to receive one of a plurality column write select signals. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33, 34, 35)
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Specification