Integrated circuit embedded with non-volatile programmable memory having variable coupling

• US 7,852,672 B2
• Filed: 11/14/2008
• Issued: 12/14/2010
• Est. Priority Date: 11/14/2007
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: Jonker LLC
• Inventors: Gross, John Nicholas, Liu, David
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/271,647
• Publication Number:
  US 20090122603A1
• Time in Patent Office: 760 Days
• Field of Search: 365/185.1
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a variable portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A programmable non-volatile device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region comprised of a first drain region and at least one separate second drain region; and

wherein the drain region overlaps a sufficient portion of said floating gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling;

further wherein the device is adapted so that different ones of said first drain region and said second drain region can be coupled to said gate during program and read operations respectively.

2. The programmable device of claim 1 wherein the device is n-channel.

3. The programmable device of claim 1 wherein the device is p-channel.

4. The programmable device of claim 1 wherein the device is adapted such that either, none or both said first drain region and said second region can be biased during a program operation, and only one of said first region and said second region are biased during a read operation.

5. The programmable device of claim 1 wherein the device is adapted such that either, none or both said first drain region and said second region can be biased during a program operation, and either or both of said first region and said second region are biased during an erase operation.

6. The programmable device of claim 1 wherein the device is adapted such that either, none or both said first drain region and said second region can be biased during a program operation, and either or both of said first region and said second region are biased during a read operation.

7. The programmable device of claim 1 wherein the device is adapted such that at least one of a program operation, a read operation, and/or an erase operation can be varied in time by changing a coupling of said first drain region and said second region to said gate.

8. The programmable device of claim 1 wherein said floating gate can be erased.

9. The programmable device of claim 8 wherein said device can be re-programmed.

10. The programmable device of claim 8 wherein said floating gate is eraseable by an erase voltage applied to said source region.

11. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

12. The programmable device of claim 11 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

13. The programmable device of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

14. The programmable device of claim 13, wherein a set of second trenches in said substrate are used as embedded DRAM.

15. The programmable device of claim 1, further including a second programmable device coupled in a paired latch arrangement such a datum and its compliment are stored in said paired latch.

16. The programmable device of claim 1, wherein the device is adapted to be read by a bias voltage applied to one of said first drain region and/or said at least one separate second drain region which is adjusted with time to determine a threshold voltage of said floating gate.

17. The programmable device of claim 1, wherein said floating gate is a multi-level structure.

18. The programmable device of claim 1, wherein said device is part of a thin film transistor.

19. The programmable device of claim 1, wherein said floating gate is oriented in a non-planar configuration.

20. The programmable device of claim 1, wherein said floating gate is distributed and includes impurities acting as charge storage sites.

21. A one-time programmable (OTP) device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region overlapping a portion of said floating gate, and said drain region including at least a first drain region and a second selectable drain region;

wherein a variable capacitive coupling between said drain region and said floating gate can be effectuated by one or more selection signals applied to said first drain region and said second drain region respectively;

wherein said variable capacitive coupling causes a variable amount of channel hot electrons from said first drain region and from said second drain region to permanently alter a threshold value of said floating gate and store data in the OTP device.