Three dimensional stacked nonvolatile semiconductor memory
First Claim
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1. A three dimensional stacked nonvolatile semiconductor memory comprising:
- a semiconductor substrate;
a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and
a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction,wherein each of the first and second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least three conductive layers by being insulated therefrom, and columnar semiconductors having lower ends connected to the semiconductor substrate and upper ends connected to the bit line and passing through the at least three conductive layers,wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, and remaining conductive layers excluding the uppermost layer of the at least three conductive layers have a plate shape whose width in the first direction is larger than the width in the first direction of the first select gate lines,wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively and memory cells are comprised of the word line and the columnar semiconductor, respectively, andwherein the first select gate lines in the first block and the first select gate lines in the second block are connected to the first driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.
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Abstract
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.
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Citations
20 Claims
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1. A three dimensional stacked nonvolatile semiconductor memory comprising:
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a semiconductor substrate; a memory cell array comprised of first and second blocks disposed on the semiconductor substrate side by side in a first direction; and a first driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction, wherein each of the first and second blocks is comprised of at least three conductive layers stacked on the semiconductor substrate by being insulated from each other, a bit line disposed on the at least three conductive layers by being insulated therefrom, and columnar semiconductors having lower ends connected to the semiconductor substrate and upper ends connected to the bit line and passing through the at least three conductive layers, wherein an uppermost layer of the at least three conductive layers is comprised of first select gate lines extending in the second direction, a lowermost layer of the at least three conductive layers is a second select gate line, remaining conductive layers excluding the uppermost layer and the lowermost layer of the at least three conductive layers are a word line, and remaining conductive layers excluding the uppermost layer of the at least three conductive layers have a plate shape whose width in the first direction is larger than the width in the first direction of the first select gate lines, wherein select gate transistors are comprised of the first select gate lines and the columnar semiconductors, and the second select gate line and the columnar semiconductors, respectively and memory cells are comprised of the word line and the columnar semiconductor, respectively, and wherein the first select gate lines in the first block and the first select gate lines in the second block are connected to the first driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A three dimensional stacked nonvolatile semiconductor memory comprising:
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a memory cell array which includes first and second blocks; a select gate line which is connected to a gate of a first select gate transistor in the first block and a gate of a second select gate transistor in a second block; and a driver which includes a first switch supplying a first signal to the select gate line and a second switch supplying a second signal to the select gate line, wherein the first switch turns on, the second switch turns off and the first signal is supplied to the select gate line, when one of the first and second blocks is selected, and the first switch turns off, the second switch turns on and the second signal is supplied to the select gate line, when both of the first and second blocks is unselected.
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Specification