High-speed receiver architecture

• US 7,852,913 B2
• Filed: 11/14/2006
• Issued: 12/14/2010
• Est. Priority Date: 10/03/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: ClariPhy Communications Incorporated (Inphi Corporation)
• Inventors: Hueda, Mario R., Carrer, Hugo S., Crivelli, Diego E., Luna, German C., Agazzi, Oscar E., Grace, Carl
• Primary Examiner(s): Ahn; Sam K
• Application Number:
  US11/559,850
• Publication Number:
  US 20070133719A1
• Time in Patent Office: 1,491 Days
• Field of Search: 375229-236, 375/259, 375/316, 375/324, 375/341, 375/350, 379/387.02, 379/340, 379/398, 324/607, 341/126, 341/127, 341/128, 341/155, 341/156, 341/159, 333/18, 333/28.R, 708/300, 708/322, 708/323
• US Class Current: 375/229
• CPC Class Codes: H03M 1/0626 by filtering
• CPC Class Codes: H03M 1/1004 without interrupting normal operation, e.g. by providing an additional component for temporarily replacing components to be tested or calibrated H03M1/1009, H03M1/1071 take precedence
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H04B 10/6971 using equalisation
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 2025/03356 Baseband transmission
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 25/025 using least-mean-square [LMS] method
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03184 Details concerning the metric
• CPC Class Codes: H04L 25/03292 with channel estimation circuitry

Abstract

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Claims

1. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels, wherein the interleaved ADC is based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline; and

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels,

wherein the multi-channel equalizer has a same or higher degree of parallelism as the interleaved ADC, and

wherein the ADC channels are further demultiplexed before being received by the multi-channel equalizer.

2. The receiver of claim 1 wherein the multi-channel equalizer comprises:

a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator.

3. The receiver of claim 2 wherein the FFE and/or the channel estimator for the Viterbi decoder are adapted on a sub-sampled basis using an LMS algorithm.

4. The receiver of claim 1 wherein the multi-channel equalizer applies an equalization that includes both a term based on shared coefficients for all ADC channels and another term based on channel-dependent coefficients.

5. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels, wherein the interleaved ADC is based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline; and

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels.

6. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels;

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels; and

a timing recovery circuit coupled to receive an output of the interleaved ADC and an error signal from the multi-channel equalizer, for driving a clock for the interleaved ADC,

wherein the timing recovery circuit comprises a pulse preprocessor that adapts to a time-varying impulse response of a communications channel.

7. A transceiver chip for 10 G or higher fiber optic communication, comprising the following integrated on a single integrated circuit:

a host interface for receiving 10 G electrical digital data in a host format and for transmitting 10 G electrical digital data in a host format;

a laser driver port for generating an electrical signal modulated by 10 G data and suitable for driving a laser driver;

transmit path circuitry coupled between the host interface and the laser driver port;

a TIA port for receiving an electrical signal modulated by 10 G data from a transimpedance amplifier; and

receive path circuitry coupled between the TIA port and the host interface, the receive path circuitry comprising an interleaved analog to digital converter (ADC) having N analog to digital converter (ADC) channels for receiving the 10 G electrical signal from the TIA port, where N is an integer, the interleaved ADC based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline, and a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels.

8. The transceiver chip of claim 7 wherein the receive path circuitry further comprises:

a programmable gain amplifier that applies a variable gain to the 10 G electrical signal from the TIA port;

a multi-stage automatic gain control coupled between the interleaved ADC, the multi-channel equalizer and the programmable gain amplifier, for applying a variable gain to the programmable gain amplifier; and

a timing recovery circuit coupled to receive an output of the interleaved ADC and an error signal from the multi-channel equalizer, for driving a clock for the interleaved ADC.

9. The transceiver chip of claim 7, wherein the multi-channel equalizer comprises:

a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator.

10. The transceiver chip of claim 9, wherein the FFE or the channel estimator for the Viterbi decoder is adapted on a sub-sampled basis using an LMS algorithm.

11. The transceiver chip of claim 7, wherein the multi-channel equalizer applies an equalization that includes both a term based on shared coefficients for all ADC channels and another term based on channel-dependent coefficients.