Output stage for a hearing aid and method of driving output stage

• US 7,853,029 B2
• Filed: 08/07/2006
• Issued: 12/14/2010
• Est. Priority Date: 02/08/2004
• Status: Active Grant

• Current Assignee: Widex A/S (WS Audiology A/S)
• Original Assignee: Widex A/S (WS Audiology A/S)
• Inventors: Jensen, Lars Baekgaard
• Primary Examiner(s): Ni; Suhan
• Application Number:
  US11/499,769
• Publication Number:
  US 20070036375A1
• Time in Patent Office: 1,590 Days
• Field of Search: 381/312, 381316-318, 381/111, 381/23.1, 381320-321
• US Class Current: 381/312
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H04R 2460/03 Aspects of the reduction of energy consumption in hearing devices
• CPC Class Codes: H04R 25/505 using digital signal processing

Abstract

In an output stage for a hearing aid (62), a reduction in the power consumption for low level input signals is obtained through the use of a time-averaging output driver (42), whereby the output transducer is subject to three different conditions of operations, this being obtained through the generation of three-state control signals for control of a H-bridge. The three-state control signals are generated through the use of a time-averaging device whereby the two-level output of a single bit Sigma-Delta modulator (21) is transformed to a set of control signals that, at any given time, can assume one of three states. In a preferred embodiment the time-averaging device is a delay (40).

Claims

1. An output stage for a hearing aid, said hearing aid comprising an input transducer device, an AD-converter, a digital signal processor, a single bit Sigma-Delta modulator, an output driver and an output transducer, said output driver having an H-bridge with two branches, each branch having a respective output terminal for connection to the output transducer, a first one of the branches being controlled by a first binary control signal, and a second one of the branches being controlled by a second binary control signal, which second binary control signal is derived as a time-delayed version of the first binary control signal.

2. The output stage according to claim 1, wherein the output driver is implemented in CMOS technology.

3. The output stage according to claim 1, wherein the time-delayed version of the first binary control signal is obtained by use of a clocked delay.

4. The output stage according to claim 3, wherein the clocked delay comprises a clocked inverter.

5. The output stage according to claim 3, wherein the clocked delay comprises a clocked, inverting flip-flop.

6. The output stage according to claim 1, wherein the output driver comprises an averaging filter adapted for performing a time-averaging function.

7. A hearing aid comprising an input transducer device, an AD-converter, a digital signal processor and an output stage, said output stage comprising a single bit Sigma-Delta modulator and an output transducer, said output stage further comprising an output driver, said output driver having an H-bridge with two branches, each branch having a respective output terminal for connection to the output transducer, a first one of the branches being controlled by a first binary control signal, and a second one of the branches being controlled by a second binary control signal, which second binary control signal is derived as a time-delayed version of the first binary control signal.

8. A method of driving an output transducer in a hearing aid, comprising

producing a first binary control signal,

producing a second binary control signal in the form of a delayed version of the first binary control signal,

selecting an H-bridge having a first branch and a second branch,

connecting a respective output terminal of each of said first and said second branch with a respective terminal of the output transducer,

controlling said first branch by the first binary control signal, and

controlling said second branch by the second binary control signal.

9. The method according to claim 8, wherein the delayed version of the first binary control signal is delayed by one clock-pulse.

10. The method according to claim 8, wherein said first branch is a non-inverting branch, and wherein said second branch employs an inverter-delay combination to invert and delay said first binary control signal in order to derive said second binary control signal.