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Parallel testing in a per-pin hardware architecture platform

  • US 7,853,425 B1
  • Filed: 07/11/2008
  • Issued: 12/14/2010
  • Est. Priority Date: 07/11/2008
  • Status: Expired due to Fees
First Claim
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1. A measurement system for testing a device under test (DUT), said system comprising:

  • a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT;

    a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing devices on the DUT;

    a scheduler component for designating at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test;

    a controller operable to read and execute said computer-executable instructions, said controller initiating the first test and the second test to be conducted in parallel and initiating at least a third test sequentially after at least one of the first and second tests wherein said first test, said second test and said third test may or may not be unique and the scheduler component comprises;

    a query component for identifying from the computer-executable instructions defining the first and second tests a testing device resource to be utilized in conducting each of the first and second tests;

    a comparison component for comparing the testing device resource to be utilized in conducting the first test to the testing device resource to be utilized in conducting the second test; and

    a logic component for determining that the testing device resource to be utilized in conducting the first test does not conflict with the testing device resource to be utilized in conducting the second test.

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