Locating hold time violations in scan chains by generating patterns on ATE

• US 7,853,846 B2
• Filed: 10/31/2007
• Issued: 12/14/2010
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Winblad, Gary A., Cannon, Stephen A., Dokken, Richard C., Crouch, Alfred L.
• Primary Examiner(s): Trimmings; John P
• Application Number:
  US11/931,847
• Publication Number:
  US 20090113265A1
• Time in Patent Office: 1,140 Days
• Field of Search: None
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318525 Test of flip-flops or latches
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass

Abstract

A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.

Claims

1. A method for determining if a scan chain is blocked under all environmental conditions comprising the following steps;

setting an environmental variable of a device under test wherein the environmental variable comprises at least one of temperature and supply voltage;

repeatedly applying a non-constant sequence pattern to the device under test;

sweeping the environmental variable through a range while repeating the steps preceding;

recording a value of the environmental variable which enables a match of an input sequence to the device under test and an output sequence from the device under test, whereby no changes in the output sequence distinguishes the scan chain as broken, an exact match of the input sequence and the output sequence distinguishes the scan chain as good, and variability in matching input sequences and output sequences distinguishes the scan chain as potentially having defects causing hold time violations in at least one scan cell in the scan chain; and

determining a number of scan cells in the scan chain having defects causing hold time violations by,

setting the environmental variable to a value determined to cause a potential hold time violation; and

then

applying a pattern of 2n ones, 2n zeroes and n ones to an input of the scan chain, wherein n is the length of the scan chain; and

observing an output of the scan chain and comparing a number of clocks to a number of bits between transitions, whereby the number of scan cells causing hold time violations is equal to the number of clocks that a transition occurs before n clocks.

2. The method of claim 1 further comprising a method for localizing a defect causing a hold time violation to a scan cell in the scan chain comprising the steps following:

setting the environmental variable to a safe value wherein the safe value is one determined to enable an exact match of the input and output sequences;

applying at least one of four phase patterns for n cycles wherein the phase patterns are 00110011, 01100110, 11001100, and 10011001, (repeating hexadecimal 3'"'"'s 6'"'"'s, C'"'"'s and 9'"'"'s);

setting the environmental variable to a value associated with a hold time violation;

clocking once;

setting the environmental variable to the safe value as before;

clocking n bits and observing m bits, wherein n is the longest chain length on the device and m is an individual scan chain length; and

comparing the applied phase pattern with the output sequence;

whereby the bit number of non-matching bits corresponds to the position of a victim scan cell in the scan chain caused by the hold time violation.

3. An apparatus comprising a tester and a processor adapted to apply signals to a device under test according to a program tangibly embodied as instructions encoded on computer readable media according to claim 1.

4. A method for determining the number of scan cells in a scan chain having a defect causing a hold time violation comprising the steps following:

setting an environmental variable to a value determined to cause a potential hold time violation;

applying a pattern having i) background of logic zeros followed by a foreground of logic ones, and ii) a background of logic ones followed by a foreground of logic zeros;

observing the output of the scan chain and comparing a number of clocks to a number of bits between transitions, whereby the number of hold time violations is equal to the number of clocks a transition occurs before n wherein n is the length of the scan chain.

5. The method of claim 4, wherein:

the background of logic zeros followed by the foreground of logic ones is a background of 2n logic zeros followed by a foreground of n logic ones; and

the background of logic ones followed by the foreground of logic zeros is a background of 2n logic ones followed by a foreground of n logic zeros.

6. A method for localizing a hold time fault in a scan chain of a device under test using automated test equipment, comprising:

using the automated test equipment,

detecting a hold time fault in the scan chain of the device under test,

determining a safe voltage value for loading and unloading the scan chain, and

localizing the hold time fault in the scan chain by applying recurring hexadecimal 3'"'"'s, 6'"'"'s, 9'"'"'s, and C'"'"'s to an input port of the scan.