Multi-layer cyclic redundancy check code in wireless communication system

• US 7,853,857 B2
• Filed: 09/14/2007
• Issued: 12/14/2010
• Est. Priority Date: 09/14/2007
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola Mobility, Inc. (Lenovo Group Ltd.)
• Inventors: Buckley, Michael E., Nimbalker, Ajit, Stewart, Kenneth A., Classon, Brian K., Blankenship, Yufei W.
• Primary Examiner(s): Abraham; Esaw T
• Application Number:
  US11/855,637
• Publication Number:
  US 20090077447A1
• Time in Patent Office: 1,187 Days
• Field of Search: 714/755, 714/781, 714/807
• US Class Current: 714/781
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0065 Serial concatenated codes

Abstract

A wireless communication device including a first CRC coder that generates a first block of CRC parity bits on a transport block and associates the first block of CRC parity bits with the transport block, a segmenting entity that segments the transport block into multiple code blocks after associating, and a second coder that generates a second block of CRC parity bits on each code block and associates a second block of CRC parity bits with each code block. The first and second blocks of CRC parity bits are based on first and second generator polynomials.

Claims

1. A wireless communication device comprising:

a first cyclic redundancy check CRC coder configured to generate a first block of CRC parity bits on a transport block, the first block of CRC parity bits based on a first generator polynomial, the first CRC coder associating the first block of CRC parity bits with the transport block;

a segmenting entity having an input coupled to the first CRC coder, the segmenting entity configured to segment the transport block into multiple code blocks after associating;

a second CRC coder configured to generate a second block of CRC parity bits on each code block, each of the second block of CRC parity bits are based on a second generator polynomial, the second CRC coder associating a second block of CRC parity bits with each code block, the second block of CRC parity bits associated with each code block is the second block of CRC parity bits generated based on the corresponding code block;

the second generator polynomial is different than the first generator polynomial;

a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits.

2. The device of claim 1, wherein the first and second generator polynomials having a common degree.

3. The device of claim 1, wherein the first and second generator polynomials have at least one different factor.

4. The device of claim 3, wherein the first and second generator polynomials share no factors.

5. The device of claim 3, wherein the first and second generator polynomials share a factor of (D+1).

6. The device of claim 1, the first and second generator polynomials having different sets of polynomial coefficients.

7. The device of claim 1, selecting the first and second generator polynomials from a group of generator polynomials comprising:

D²⁴+D²³+D⁶+D⁵+D+1;

D²⁴+D²¹+D²⁰+D¹⁷+D¹⁵+D¹¹+D⁹+D⁸+D⁶+D⁵+D+1; and

D²⁴+D²³+D¹⁸+D¹⁷+D¹⁴+D¹¹+D¹⁰+D⁷+D⁶+D⁵+D⁴+D³+D+1.

8. The device of claim 1, wherein the first generator polynomial is D²⁴+D²³+D⁶+D⁵+D+1.

9. The device of claim 1, wherein the second generator polynomial is D²⁴+D²³+D⁶+D⁵+D+1.

10. A method in a wireless communication transmitter, the method comprising:

generating, at the transmitter, a first block of first cyclic redundancy check CRC parity bits on a transport block, the first block of CRC parity bits based on a first generator polynomial;

associating the first block of CRC parity bits with the transport block;

segmenting the transport block into multiple code blocks after associating;

generating, at the transmitter, a second block of CRC parity bits on each code block, each of the second block of CRC parity bits based on a second generator polynomial, the second generator polynomial is different than the first generator polynomial;

associating a second block of CRC parity bits with each code block, the second block of CRC parity bits associated with each code block is the second block of CRC parity bits generated based on the corresponding code block;

channel encoding, at the transmitter, each of the code blocks including the associated second block of CRC parity bits;

concatenating the code blocks after channel encoding.

11. A method in a wireless communication receiver, the method comprising:

disassociating, at the receiver, a second block of cyclic redundancy check CRC parity bits associated with each of a plurality of received code blocks, the second block of CRC parity bits are generated based on a second generator polynomial and based on the corresponding code block with which the second block of CRC parity bits are associated;

forming, at the receiver, an estimated transport block having a first block of CRC parity bits associated with the estimated transport block by concatenating the code blocks after removing the associated second block of CRC parity bits, wherein the first block of CRC parity bits associated with the transport block is based on a first generator polynomial that is different than the second generator polynomial,

performing, at the receiver, a CRC check on the estimated transport block based on the first generator polynomial.

12. The method of claim 11, wherein a CRC check is performed on the plurality of code blocks before performing the CRC check on the estimated transport block.

13. The method of claim 12, wherein the CRC check on the estimated transport block is performed only if the CRC check on the plurality of code blocks does not detect any errors.

14. A method in a wireless communication transmitter, the method comprising:

generating, at the transmitter, a first block of cyclic redundancy check CRC parity bits on a transport block, the first block of CRC parity bits generated based on a generator polynomial;

associating the first block of CRC parity bits with the transport block;

interleaving the transport block after associating;

segmenting the interleaved transport block into multiple code blocks;

generating, at the transmitter, a second block of CRC parity bits on each code block, each of the second block of CRC parity bits are generated based on the generator polynomial;

associating a second block of CRC parity bits with each code block, the second block of CRC parity bits associated with each code block is the second block of CRC parity bits generated based on the corresponding code block;

channel encoding, at the transmitter, each of the code blocks including the associated second block of CRC parity bits;

concatenating the code blocks after channel encoding.

15. The method of claim 14, wherein interleaving the transport block is performed at bit level.

16. The method of claim 14, wherein interleaving the transport block is performed by permuting groups wherein each group contains a plurality of bits.

17. The method of claim 14, wherein

interleaving the transport block after associating the first block of CRC parity bits and segmenting the interleaved transport block into multiple code blocks after associating the first block of CRC parity bits is equivalent to

segmenting the transport block into multiple code blocks after associating the first block of CRC parity bits and interleaving the code blocks individually.