Method and apparatus for performing path-level skew optimization and analysis for a logic design

• US 7,853,911 B1
• Filed: 11/04/2005
• Issued: 12/14/2010
• Est. Priority Date: 11/04/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Fung, Ryan, Karchmer, David, Betz, Vaughn
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US11/267,655
• Time in Patent Office: 1,866 Days
• Field of Search: 716/2, 716/6, 716/10, 716/12, 716/13, 716/17, 713/503, 326/28, 326/39, 326/93, 326/96
• US Class Current: 716/113
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed.

Claims

1. A method for designing a system, comprising:

optimizing path-level skew in the system by generating connection-level long-path and short-path skew slacks for one or more skew domains given one of a tolerable maximum skew and a tolerable deviation from a skew schedule for each skew domain; and

performing one of synthesis, placement, and routing of the system on a target device using a strategy generated from the optimized path-level skew, wherein at least one of the optimizing and performing procedures is performed by a processor.

2. The method of claim 1, wherein generating connection-level long-path and short-path skew slacks comprises assuming intra-corner delay variation.

3. The method of claim 1, wherein generating connection-level long-path and short-path skew slacks comprises using amalgamated timing data from more than one timing corner.

4. The method of claim 1, wherein generating the connection-level long-path and short-path skew slacks comprises identifying a longest path delay in a skew domain.

5. The method of claim 4, wherein identifying the longest path delay in a skew domain comprises performing a traversal of a timing graph.

6. The method of claim 4, wherein identifying the longest path delay in a skew domain comprises using minimum achievable delays or minimum achievable delay estimates for components and connections in the system.

7. The method of claim 6, wherein the minimum achievable delays or minimum achievable delay estimates are determined to satisfy short-path timing constraints.

8. The method of claim 4, wherein a longest path delay is identified for each timing corner from a multiplicity of timing corners, for each skew domain.

9. The method of claim 1, further comprising identifying an absolute maximum target delay for the skew domain and an absolute minimum target delay for the skew domain.

10. The method of claim 9, further comprising generating the connection-level long-path skew slacks from a long-path timing analysis based on a set of connection delays and the absolute maximum target delay for the skew domain.

11. The method of claim 9, further comprising generating the connection-level short-path skew slacks from a short-path timing analysis based on a set of connection delays and the absolute minimum target delay for the skew domain.

12. The method of claim 9, further comprising generating the absolute maximum target delay based on a longest path delay identified for the skew domain.

13. The method of claim 12, further comprising generating the maximum target delay to be greater than or equal to the longest path delay identified for the skew domain.

14. The method of claim 12, further comprising increasing the maximum target delay to improve the likelihood of satisfying the maximum target delay.

15. The method of claim 12, further comprising increasing the maximum target delay to satisfy short-path timing constraints.

16. The method of claim 12, further comprising minimizing the maximum target delay to decrease the absolute skew of the final system due to percentage error in delay modeling.

17. The method of claim 12, further comprising decreasing the maximum target delay to satisfy long-path timing constraints.

18. The method of claim 9, further comprising generating the minimum target delay based on the maximum target delay and the tolerable maximum skew or tolerable deviation from the skew schedule.

19. The method of claim 9, further comprising generating minimum and maximum target delays based on the longest path delays computed for more than one timing corner, for each skew domain.

20. The method of claim 19, further comprising generating one minimum and maximum target delay pair for each timing corner from a multiplicity of timing corners to maximize a valid timing window that considers all relevant corners.

21. The method of claim 1, further comprising generating maximum and minimum delay budgets from connection-level long-path and short-path skew slacks.

22. The method of claim 1, wherein optimizing the path-level skew is performed with respect to synthesis.

23. The method of claim 1, wherein optimizing the path-level skew is performed with respect to mapping.

24. The method of claim 1, wherein optimizing the path-level skew is performed with respect to placement.

25. The method of claim 1, wherein optimizing the path-level skew is performed with respect to routing.

26. The method of claim 1, wherein the system being designed is a logic design.

27. The method of claim 26, wherein the logic design is to be implemented in a field-programmable gate array (FPGA).

28. The method of claim 1, wherein optimizing the path-level skew is performed with respect to multiple timing corners.

29. The method of claim 1, wherein optimizing the path-level skew is performed with respect to intra-corner delay variation.

30. An article of manufacture comprising a machine accessible non-transitory medium including sequences of instructions, the sequences of instructions including instructions which when executed cause the machine to perform:

optimizing path-level skew in a system by generating connection-level long-path and short-path skew slacks for one or more skew domains; and

performing one of synthesis, placement, and routing of the system on a target device using a strategy generated from the optimized path-level skew.

31. The article of manufacture of claim 30, wherein generating the connection-level long-path and short-path skew slacks for one or more skew domains is achieved given a tolerable maximum skew or a tolerable deviation from a skew schedule for each skew domain.

32. The article of manufacture of claim 31, wherein generating connection-level long-path and short-path skew slacks comprises assuming intra-corner delay variation.

35. The article of manufacture of claim 30, wherein the system is a logic design implemented on a field programmable gate array.

33. A method for designing a system, comprising:

generating connection-level long-path and short-path skew slacks for one or more skew domains given one of a tolerable maximum skew and a tolerable deviation from a skew schedule for the one or more skew domains;

generating maximum and minimum delay budgets from the connection-level long-path and short-path skew slacks; and

performing one of synthesis, placement, and routing of the system on a target device using a strategy generated from the maximum and minimum delay budgets, wherein at least one of the generating and performing procedures is performed by a processor.

34. The method of claim 33, further comprising identifying an absolute maximum target delay for the one or more skew domains and an absolute minimum target delay for the one or more skew domains.

36. The method of claim 33, wherein the system is a logic design implemented on a field programmable gate array.