Integrated circuit package system with an encapsulant cavity and method of fabrication thereof

• US 7,855,100 B2
• Filed: 03/27/2008
• Issued: 12/21/2010
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Chow, Seng Guan, Han, Byung Joon, Ramakrishna, Kambhampati, Shim, Il Kwon
• Primary Examiner(s): Chambliss; Alonzo
• Application Number:
  US12/057,299
• Publication Number:
  US 20080179729A1
• Time in Patent Office: 999 Days
• Field of Search: None
• US Class Current: 438/107
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

Claims

1. A method for fabricating an encapsulant cavity integrated circuit package system comprising:

forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, the interposer having an integrated circuit electrically connected to and on a top thereof;

attaching a component on the interposer in the encapsulant cavity wherein forming the first integrated circuit package comprises;

mounting a second integrated circuit package on the interposer in the encapsulant cavity;

mounting a third integrated circuit package on a substrate;

attaching a spacer on the third integrated circuit package; and

mounting the first integrated circuit package on the spacer.

2. The method as claimed in claim 1 wherein attaching the component comprises attaching system device packages having surface-mount package technology.

3. The method as claimed in claim 1 wherein attaching the component comprises attaching system devices having chip-scale package technology.

4. A method for fabricating an encapsulant cavity integrated circuit package system comprising:

mounting a first integrated circuit on a first surface of an interposer, the interposer having an integrated circuit electrically connected to and on a top thereof;

molding a first encapsulant over the first integrated circuit forming a first integrated circuit package;

mounting the first integrated circuit package with an inverted bottom terminal over a substrate;

molding a second encapsulant over the first integrated circuit package with the inverted bottom terminal and the substrate forming an encapsulant cavity having a second surface of the interposer substantially exposed; and

mounting a component on the second surface of the interposer in the encapsulant cavity.

5. The method as claimed in claim 4 wherein mounting the component comprises mounting passive devices on the second surface of the interposer in the encapsulant cavity.

6. The method as claimed in claim 4 wherein mounting the component comprises attaching a leaded package on the second surface of the interposer in the encapsulant cavity.

7. The method as claimed in claim 4 wherein mounting the component comprises attaching a leadless package on the second surface of the interposer in the encapsulant cavity.

8. The method as claimed in claim 4 wherein mounting the component comprises:

mounting an optical sensor device on the second surface of the interposer in the encapsulant cavity; and

attaching an optical lid over the optical sensor device and the encapsulant cavity.

9. An encapsulant cavity integrated circuit package system comprising:

a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, the interposer having an integrated circuit electrically connected to and on a top thereof;

a component on the interposer in the encapsulant cavity wherein the first integrated circuit package comprises;

a second integrated circuit package on the interposer in the encapsulant cavity;

a third integrated circuit package on a substrate;

a spacer on the third integrated circuit package; and

the first integrated circuit package on the spacer.

10. The system as claimed in claim 9 wherein the component comprises system device packages having surface-mount package technology.

11. The system as claimed in claim 9 wherein the component comprises system devices having chip-scale package technology.

12. The system as claimed in claim 9 wherein the first integrated circuit package includes a first integrated circuit on a first surface of an interposer, and wherein the component is on the second surface of the interposer in the encapsulant cavity;

and

further comprising;

a first encapsulant over the first integrated circuit forming a first integrated circuit package;

the first integrated circuit package with an inverted bottom terminal over a substrate; and

a second encapsulant over the first integrated circuit package with the inverted bottom terminal and the substrate forming an encapsulant cavity having a second surface of the interposer substantially exposed.

13. The system as claimed in claim 12 wherein the component comprises passive devices on the second surface of the interposer in the encapsulant cavity.

14. The system as claimed in claim 12 wherein the component comprises a leaded package on the second surface of the interposer in the encapsulant cavity.

15. The system as claimed in claim 12 wherein the component comprises a leadless package on the second surface of the interposer in the encapsulant cavity.

16. The system as claimed in claim 12 wherein the component comprises:

an optical sensor device on the second surface of the interposer in the encapsulant cavity; and

an optical lid over the optical sensor and the encapsulant cavity.