Formation of high sheet resistance resistors and high capacitance capacitors by a single polysilicon process

• US 7,855,422 B2
• Filed: 05/31/2006
• Issued: 12/21/2010
• Est. Priority Date: 05/31/2006
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Tai, Sung-Shan, Hu, YongZhong
• Primary Examiner(s): Warren; Matthew E
• Application Number:
  US11/444,852
• Publication Number:
  US 20070281418A1
• Time in Patent Office: 1,665 Days
• Field of Search: 257/300, 257/379, 257/380, 257/528, 257/532, 257/533, 257/536, 257/E27.016, 257/E29.343
• US Class Current: 257/379
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: Y10S 438/957 Making metal-insulator-metal device

Abstract

A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.

Claims

1. A semiconductor device comprising:

a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer disposed directly below and contacting a metal conductive layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure wherein said SAB layer blocks and insulates said metal conductive layer and said metal conductive layer laterally extends beyond said SAB layer as a continuous layer constituting a salicided layer of said metal conductive layer wherein said salicide layer of said metal conductive layer functioning as an electrode contact layer to electrically connect said top conductive layer of said capacitor to an external electrode.

2. The semiconductor device of claim 1 wherein:

said polysilicon layer is further differentially doped to form said resistor as a high sheet rho resistor of said semiconductor device.

3. The semiconductor device of claim 1 wherein:

said polysilicon layer further doped with transistor gate doping ions to form a gate for said transistor of said semiconductor device.

4. The semiconductor device of claim 1 wherein:

said transistor further comprising a gate polysilicon and said resistor further comprising a doped polysilicon resistor, wherein said gate polysilicon, said doped polysilicon resistor and said doped polysilicon layer functioning as a bottom conductive layer of said capacitor are formed by one polysilicon deposition process and disposed substantially on a same vertical level in said semiconductor device.

5. The semiconductor device of claim 1 wherein:

said capacitor and resistor are disposed on a field oxide layer disposed on a semiconductor substrate and said transistor is disposed directly on said semiconductor substrate.

6. The semiconductor device of claim 1 wherein:

said transistor further includes an electrostatic discharge (ESD) protection layer formed on top of a diffusion resistor layer connected to a source or a drain region of said transistor; and

said metal salicide layer comprising a TiSi layer electrically connected to a tungsten plug filled in a trench opened through an inter-layer dielectric layer covering said semiconductor device.

7. The semiconductor device of claim 1 wherein:

said doped polysilicon layer of said capacitor comprising an N+ doped polysilicon layer to function as a bottom conductive layer.

8. The semiconductor device of claim 1 wherein:

said capacitor further comprising a spacer surrounding and insulating said doped polysilicon layer to function as a bottom conductive layer.

9. The semiconductor device of claim 1 wherein:

said metal layer functioning as said top conductive layer of said capacitor further comprises a Ti/TiN layer and said salicided layer of said metal conductive layer comprises a TiSi layer extends continuously from said Ti/TiN layer.

10. The semiconductor device of claim 7 wherein:

said N+ doped polysilicon layer functioning as said bottom conductive layer of said capacitor is in electrical contact with a tungsten plug filling in a trench opened through an inter-layer dielectric layer covering said semiconductor device.

11. The semiconductor device of claim 1 wherein:

said resistor includes a high resistive element comprising a doped resistive polysilicon segment wherein both ends of said resistive polysilicon element comprising contact head segments comprising N+ doped segments on both ends of the polysilicon segment; and

said contact head segments are further in contact with a tungsten plug filling in a trench opened through an inter-layer dielectric layer covering said semiconductor device.

12. The semiconductor device of claim 1 wherein:

said resistor further includes a spacer layer for surrounding and insulting said high resistive element from said capacitor.