Lock and key through-via method for wafer level 3 D integration and structures produced

• US 7,855,455 B2
• Filed: 09/26/2008
• Issued: 12/21/2010
• Est. Priority Date: 09/26/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Purushothaman, Sampath, Shahidi, Ghavam Ghavami, Rothwell, Mary E., Yu, Roy Rongqing
• Primary Examiner(s): Smith; Zandra
• Assistant Examiner(s): Patton; Paul E
• Application Number:
  US12/239,688
• Publication Number:
  US 20100078770A1
• Time in Patent Office: 816 Days
• Field of Search: 257/750, 257/758, 257/760, 257/762, 257/764, 257/773, 257/774, 257/784, 257/E23.01, 257/E23.011, 257/E23.012, 438/106, 438/107, 438/118
• US Class Current: 257/750
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13611 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13657 : Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16111 : the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16112 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16147 : the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/24051 : Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24146 : the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/25105 : Connecting at different heights
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81903 : by means of a layer connector
• CPC Class Codes: H01L 2224/82031 : by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82047 : by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/821 : Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83097 : Heating
• CPC Class Codes: H01L 2224/83121 : Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/83141 : Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/83194 : Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83208 : applying unidirectional static pressure
• CPC Class Codes: H01L 2224/83209 : applying isostatic pressure, e.g. degassing using vacuum or a pressurised liquid
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9211 : Parallel connecting processes
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/90 : Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

Claims

1. A structure comprising two device layers joined together to form an electronic system and further comprising:

a first device layer disposed on a first substrate and comprising a first set of circuits and interconnect wiring;

a second device layer disposed on a second substrate and comprising a second set of circuits and interconnect wiring;

said first and said second device layers further connected using two sets of via connections comprising a first set of via connections that extend from below the top surface of said first device layer to the top surface of said second device layer and a second set of via connections that extend from said top surface of said first device layer through said second device layer, said second substrate and connecting to interconnect layers and input output terminals disposed on the back side of said second substrate;

said structure further comprising an adhesive layer disposed between said top surface of said first device layer and said top surface of said second device layer and surrounding a portion of the height of said first and said second via connections; and

further comprising an passivation coating to protect the sidewalls of said first and second sets of vias in said portions where they are surrounded by said adhesive layer.

2. A structure according to claim 1 further comprising at least one more device layer in the manner of said second device layer, stacked on and attached to the back side of said second device layer and connected to said first and said second device layers and said input output terminal by means of additional via connections.

3. A structure according to claim 1 wherein said circuits in said first and second device layer comprise any one of logic circuits, memory circuits, controller circuits, image processing circuits, optoelectronic circuits and combinations thereof.

4. A structure according to claim 1 wherein said interconnect layers in said second device layer comprise dual damascene wiring and vias, through substrate vias and combinations thereof.

5. A structure according to claim 1 wherein said first and second substrates comprise silicon, or gallium arsenide, or silicon carbide.

6. A structure according to claim 1 wherein said adhesive layer comprises a polyimide adhesive, or benzocyclobutene adhesive, or polyarylene ether adhesive, or epoxy adhesive.

7. A structure according to claim 1 wherein said through vias comprise electrically conductive Al, Mo, W, Cu, Au, Ag, Pd, Pt, Ni, or combinations thereof.