Memory system and method using stacked memory device dice, and system using the memory system

• US 7,855,931 B2
• Filed: 07/21/2008
• Issued: 12/21/2010
• Est. Priority Date: 07/21/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A., Jeddeloh, Joseph M., Johnson, James B.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US12/176,951
• Publication Number:
  US 20100014364A1
• Time in Patent Office: 883 Days
• Field of Search: 365/230.03, 365/233.12, 365/230.06, 365/194, 326/30
• US Class Current: 365/230.03
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.

Claims

1. A memory system, comprising:

a plurality of stacked memory device dice containing a plurality of memory cells; and

a logic die coupled to the memory device dice through a plurality of conductors, the logic die being operable to write data to and read data from the memory device dice, the logic die including a timing correction system that is operable to control the timing at which at least one signal is received by the logic die from each of the memory device dice.

2. The memory system of claim 1 wherein the plurality of stacked memory device dice are connected to each other and to the logic die through a plurality of through silicon vias.

3. The memory system of claim 1 wherein the at least one signal coupled between the logic die and each of the memory device dice comprise a respective set of read data signals transmitted to the logic die by each of the memory device dice.

4. The memory system of claim 2 wherein each of the memory device dice is operable to transmit its respective set of read data signals at a time determined by receipt of a respective read data strobe, and wherein the timing correction system comprises:

a strobe timing adjustment circuit for each of the memory device dice, each of the strobe timing adjustment circuits being structured to output a read strobe signal with a timing that is controlled by a respective timing control signal; and

a timing control circuit generating the respective timing control signals and applying the timing control signals to the respective memory device dice, the timing control circuit generating the timing control signals causing the respective sets of read data transmitted by the memory device dice to be received by the logic die with substantially the same timing.

5. The memory system of claim 4 wherein the timing control circuit is operable to generate each of the timing control signals by providing a respective plurality of timing control signals to each of the strobe timing adjustment circuits that cause the respective strobe timing adjustment circuit to vary the timing of the respective read strobe signal over a range thereby causing the respective memory device die to provide it respective set of read data signals to the logic die at times that vary over a range, the timing circuit being operable to use as the timing control signal for application to the respective strobe timing adjustment circuit a timing control signal that causes the set of read data signals to be received by the logic die at a suitable time within the range.

6. The memory system of claim 2 wherein the timing correction system comprises a plurality of data receivers each of which is operable to receive a corresponding read data signal from each of the memory device dice, the receiver being operable to deserialize the received read data signal into a plurality of parallel read data bits.

7. The memory system of claim 6 wherein each of the receivers is operable to capture the received read data signal responsive to a clock signal, all of the plurality of receivers using the same clock signal to capture their respective received read data signal.

8. The memory system of claim 6 wherein each of the receivers comprise:

a plurality of flip-flops coupled to receive the read data signal, each of the flip-flops being operable to store and apply to an output a respective sample of the read data signal;

a selector operable to generate and sequentially apply the clock signals to the respective flip-flops so that the flip-flops store the respective samples of the read data signal; and

a plurality of multiplexers each of which is coupled to the respective outputs of a plurality of the flip-flops, the multiplexers being responsive to a clock signal to alternately output the respective samples from a respective pair of the plurality of flip-flops.

9. The memory system of claim 2 wherein each of the memory device dice comprise a respective dynamic random access memory device dice.

10. A system, comprising:

a memory access device; and

a memory system coupled to the memory access device, the memory system comprising;

a plurality of stacked memory device dice containing a plurality of memory cells and being operable to transmit read data responsive to a received read strobe signal, the timing at which each of the memory device dice transmitting the read data being determined by the time of receiving the respective read strobe signal; and

a logic die coupled to the memory access device and to the memory device dice through a plurality of conductors, the logic die being operable to write data to and read data from the memory device dice, the logic die including a timing correction system that is operable to control the timing that the read strobe signals are applied to the respective memory device dice, the logic die being operable to transmit the read data to the memory access device substantially upon receipt from the memory device dice.

11. The system of claim 10 wherein the timing correction system comprises:

a strobe timing adjustment circuit for each of the memory device dice, each of the strobe timing adjustment circuits being structured to output the respective read strobe signal with a timing that is controlled by a respective timing control signal; and

a timing control circuit generating the respective timing control signals and applying the timing control signals to the respective memory device dice, the timing control circuit generating the timing control signals causing the respective sets of read data transmitted by the memory device dice to be received by the logic die with substantially the same timing.

12. The system of claim 11 wherein the timing control circuit is operable to generate each of the timing control signals by providing a respective plurality of timing control signals to each of the strobe timing adjustment circuits that cause the respective strobe timing adjustment circuit to vary the timing of the respective read strobe signal over a range thereby causing the respective memory device die to provide it respective set of read data signals to the logic die at times that vary over a range, the timing circuit being operable to use as the timing control signal for application to the respective strobe timing adjustment circuit a timing control signal that causes the set of read data signals to be received by the logic die at a suitable time within the range.

13. The system of claim 10 wherein the logic die comprises a plurality of data receivers each of which is operable to receive a corresponding read data signal from each of the memory device dice, the receiver being operable to deserialize the received read data signal into a plurality of parallel read data bits and to apply the parallel read data bits to the memory access device.

14. The system of claim 10 wherein each of the memory device dice comprise a respective dynamic random access memory device dice.

15. A method of coupling read data from a plurality of stacked memory device dice each of which is connected to a logic die, the method comprising:

transmitting respective read strobe signals to each of the memory device dice from the logic die;

transmitting read data to the logic die from each of the memory device dice responsive to the memory device dice receiving the respective read strobe signal; and

adjusting the timing of transmitting respective read strobe signals from the logic die to each of the memory device dice to cause the read data to be received by the logic die at substantially the same time from each of the memory device dice.

16. The method of claim 15 wherein the act of adjusting the timing of transmitting respective read strobe signals to each of the memory device dice comprises conducting a training sequence to determine which timing allows the logic die to suitably capture the read data.

17. The method of claim 16 wherein the training sequence comprises:

repetitively transmitting the read strobe signal to each of the memory device dice, the read strobe signals being transmitted at different times over a range of times;

receiving read data at the logic die responsive to each of the read strobe signals transmitted to each of the memory device dice;

determining which timing of each of the read strobe signals caused the read data to be received by the logic die at substantially the same time from each of the memory device dice; and

subsequently using the determined timing to transmit each of the read strobe signals to the respective memory device dice.

18. The method of claim 15 wherein the act of adjusting the timing of transmitting each of the read strobe signals to a respective one of the memory device dice comprises:

providing a read strobe signal having a plurality of serial bits;

deserializing the read strobe signal to convert the plurality of serial bits into a plurality of corresponding parallel bits; and

transmitting each of the bits to the respective memory device dice as a serial bit stream starting at a time adjusted to cause the read data to be received by the logic die at substantially the same time that respective read data from the other memory device dice are received at the logic die.

19. The method of claim 15, further comprising the respective read data from each of the memory device dice responsive to a clock signal, the same clock signal being used to capture the respective read data from all of the memory device dice.