Direct conversion receiver

• US 7,856,218 B2
• Filed: 03/20/2007
• Issued: 12/21/2010
• Est. Priority Date: 12/20/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hori, Kazuaki, Yamamoto, Akio, Tanaka, Satoshi, Akamine, Yukinori
• Primary Examiner(s): VO, NGUYEN THANH
• Application Number:
  US11/725,475
• Publication Number:
  US 20070190960A1
• Time in Patent Office: 1,372 Days
• Field of Search: 4552321-2342, 455/241.1, 455/246.1, 455/296, 455/303, 455/307, 455/312, 455/324, 375/345, 375/346
• US Class Current: 455/234.1
• CPC Class Codes: H03G 3/3052 in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

In a direct conversion receiver, to cancel a DC offset generated in the baseband processing block, negative feedback arrangements comprising a gain control amplifier and a low-pass filter are respectively attached to the I and Q signal branches of the baseband block following mixer outputs. The gain control amplifier in each negative feedback circuit is gain adjusted so that the product G·B of the gain G of a primary gain control amplifier and its own gain B will be constant and thereby the DC offset is cancelled. This DC offset cancellation can be applied in a continuous receiving system with no intermittent time during a receiving operation. Capacitance elements located off-chip can be reduced to those to be used only in the low-pass filters in the negative feedback circuits, whereas many off-chip capacitance elements have been required to be inserted between each stage of gain control amplifiers in conventional baseband chains.

Claims

1. A direct conversion receiver comprising:

a pair of mixers which convert a receive signal frequency to a baseband frequency; and

a baseband frequency signal processing block including a pair of first gain control amplifiers and a pair of first filters, following said mixers,

wherein said baseband frequency signal processing block further includes a pair of negative feedback circuits with an adjustable feedback factor, each negative feedback circuit comprising a second gain control amplifier connected to a respective first gain control amplifier of the pair of first gain control amplifiers and a second filter of low-pass type connected to the gain control second amplifier, and

wherein the second filter of each negative feedback control circuit is configured to adjust to optimize frequency characteristics and suppress degradation in a signal.

2. The direct conversion receiver according to claim 1, wherein said second filter of each negative feedback circuit is a low-pass filter with an adjustable cut-off frequency.

3. The direct conversion receiver according to claim 2, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first gain control amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first gain control amplifiers.

4. The direct conversion receiver according to claim 1, further comprising a pair of DC offset cancellation circuits, each comprising:

an analog to digital converter which is connected to an output of one of said pair of first gain control amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first gain control amplifiers.

5. The direct conversion receiver according to claim 1, wherein said pair of first gain control amplifiers have multistage compositions in which a pair of first-stage amplifiers are a pair of static gain amplifiers to which a pair of DC offset cancellation circuits are attached respectively, each said DC offset cancellation circuit comprising:

an analog to digital converter which is connected to an output of one of said pair of first gain control amplifiers to convert analog signals to digital signals;

a digital processing circuit which detects a DC offset voltage out of output signals from said analog to digital converter and calculates a voltage to cancel the DC offset voltage; and

,

a digital to analog converter which converts a digital signal of the voltage calculated by the digital processing circuit into an analog signal of the voltage and supplies the analog signal of the voltage to said one of said pair of first gain control amplifiers.