Transformer coils for providing voltage isolation

• US 7,856,219 B2
• Filed: 06/28/2007
• Issued: 12/21/2010
• Est. Priority Date: 06/03/2004
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Dupuis, Timothy
• Primary Examiner(s): Yun; Eugene
• Application Number:
  US11/770,530
• Publication Number:
  US 20080013635A1
• Time in Patent Office: 1,272 Days
• Field of Search: 455/280, 455/292, 455/67.15, 455/333, 455/338, 455/148, 455/167.1, 455/279.1, 455/286, 455/274, 375/258
• US Class Current: 455/280
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1204 : Optical Diode
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/33523 : with galvanic isolation between input and output of both the power stage and the feedback loop
• CPC Class Codes: H04L 25/0266 : Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling

Abstract

A circuit package providing voltage isolation includes at least one output and first circuitry located in a substrate of the circuit package for performing an operation. A transformer located in the metal layers of the circuit package provides voltage isolation between the first circuitry and the at least one output.

Claims

1. An integrated isolator, comprising:

first and second integrated circuit substrates;

each of said first and second substrates having contained on the surface thereof a lower transformer coil with an associated input;

each said lower transformer coil on said first and second substrates having a layer of dielectric material disposed thereover and each said lower transformer coil associated with one of a first transformer and a second transformer; and

a top conductive coupling layer disposed over each of said respective dielectric layers on said first and second substrates to couple energy from one of said inputs of said respective lower transformer coils on said first and second substrates to the other of said inputs, wherein said top conductive coupling layer comprises;

a respective upper transformer coil for each of said first and second substrates disposed over said respective lower transformer coil and separated therefrom by said associated dielectric layer, each of said upper transformer coils having an input;

each of the upper transformer coils associated with one of the first transformer and the second transformer; and

said inputs of each of said upper transformer coils on said first and second substrates, respectively, conductively connected together with a conductive medium.

2. The isolator of claim 1, wherein said top conductive coupling layer and each of said respective lower transformer coils on said first and second substrates are fabricated as an integral part of said first and second substrates.

3. The isolator of claim 1, wherein said conductive medium comprises bond wires.

4. The isolator of claim 1, wherein said upper and lower transformer coils are planar.

5. The isolator of claim 1, wherein said first and second substrates are fabricated with a CMOS process and said upper and lower transformers are fabricated in metal layers that are part of said CMOS process.

6. The isolator of claim 1, wherein said first and second substrates are mounted in an integrated circuit package.

7. The isolator of claim 6, wherein one of said first and second substrates has an interface associated therewith for interfacing between an interface pin on said integrated circuit package and the input of said associated lower transformer coil.

8. The isolator of claim 7, wherein said interface comprises a driver circuit for driving the input of said associated lower transformer coil with a signal.

9. The isolator of claim 7, wherein said interface comprises a receiver circuit for receiving from the input of said associated lower transformer coil a signal.

10. The isolator of claim 7, wherein said first and second substrates are isolated from each other.

11. The isolator of claim 1, wherein each of said first and second substrates has an interface associated therewith for interfacing between a respective first or second interface pin on said integrated circuit package and the input of said associated lower transformer coil.

12. The isolator of claim 11, wherein said interface on one of said first and second substrates comprises a driver for driving the input of said associated lower transformer coil with a signal.

13. The isolator of claim 11, wherein said interface on one of said first and second substrates comprises a receiver for receiving a signal from the input of said associated lower transformer.

14. The isolator of claim 11, wherein said interface on one of said first and second substrates comprises a driver for driving the input of said associated lower transformer coil with a signal and said interface on the of said first and second substrates comprises a receiver for receiving a signal from the input of said associated lower transformer coil.