Method for fabricating transistor with thinned channel

• US 7,858,481 B2
• Filed: 06/15/2005
• Issued: 12/28/2010
• Est. Priority Date: 06/15/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S., Radosavljevic, Marko, Kavalieros, Jack T., Doczy, Mark L., Doyle, Brian S., Brask, Justin K., Majumdar, Amlan, Metz, Matthew V., Datta, Suman
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Singal; Ankush K
• Application Number:
  US11/154,138
• Publication Number:
  US 20060286755A1
• Time in Patent Office: 2,022 Days
• Field of Search: 438/183, 438/321, 438/926, 257/E21.434, 257/E21.444, 257/E21.453
• US Class Current: 438/299
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H04B 1/3827 Portable transceivers
• CPC Class Codes: Y10S 438/926 : Dummy metallization

Abstract

A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Claims

1. A method for fabricating a transistor comprising:

defining a semiconductor body with a mask, the mask and the entire semiconductor body having essentially the same initial width; and

, subsequently,

forming a dummy gate over the body to define a channel region in the body, leaving the mask in place on at least a portion of the body covered by the dummy gate;

implanting the body to form a source and drain region;

surrounding the dummy gate with dielectric material;

removing the dummy gate;

with the mask in place, etching the channel region of the body with an etchant which etches the body without etching the mask so as to reduce the width of the body to a width less than the width of the mask, but not to reduce the height of the body disposed beneath the mask;

removing the mask; and

forming a permanent gate structure on the channel region.

2. The method defined by claim 1, wherein the implanting of the body comprises:

using a first implant in alignment with the dummy gate to form tip source and drain regions;

forming spacers on sides of the dummy gate; and

using a second implant in alignment with the spacers to form main source and drain regions.

3. The method defined by claim 2, wherein the forming of the permanent gate structure comprises forming a high-k insulation over the channel region and forming a metal gate on the insulation.

4. The method defined by claim 3, wherein the metal gate has a work function between 3.9 and 5.2 eV.

5. The method defined by claim 3, wherein the spacers comprise a carbon doped nitride.