Memory device and semiconductor device

• US 7,858,972 B2
• Filed: 04/23/2007
• Issued: 12/28/2010
• Est. Priority Date: 04/28/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tokunaga, Hajime, Kato, Kiyoshi
• Primary Examiner(s): Dang; Phuc T
• Application Number:
  US11/785,964
• Publication Number:
  US 20080083830A1
• Time in Patent Office: 1,345 Days
• Field of Search: 257/E51.008, 257/4, 257/5, 257/40, 438/29, 438/69, 438/82, 438/99
• US Class Current: 257/40
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor.

Claims

1. A memory device comprising:

a thin film transistor; and

a memory cell array including a memory cell,

wherein the memory cell comprises;

a first semiconductor film having an n-type impurity region and a p-type impurity region that are adjacent to each other;

a first conductive film which is formed over the first semiconductor film and which is connected to the n-type impurity region;

a second conductive film which is formed over the first conductive film;

an organic compound layer interposed between the first conductive film and the second conductive film; and

a third conductive film which is formed over the first semiconductor film and which is connected to the p-type impurity region, and

wherein the first semiconductor film of the memory cell is formed over the same insulating surface as a second semiconductor film of the thin film transistor.

2. A memory device comprising:

an n-channel thin film transistor;

a p-channel thin film transistor; and

a memory cell array including a memory cell,

wherein the memory cell comprises;

a first semiconductor film having an n-type impurity region and a p-type impurity region that are adjacent to each other;

a first conductive film which is formed over the first semiconductor film and which is connected to the n-type impurity region;

a second conductive film which is formed over the first conductive film; and

an organic compound layer interposed between the first conductive film and the second conductive film; and

a third conductive film which is formed over the first semiconductor film and which is connected to the p-type impurity region,

wherein the first semiconductor film of the memory cell is formed over the same insulating surface as a second semiconductor film of the n-channel thin film transistor and a third semiconductor film of the p-channel thin film transistor.

3. The memory device according to claim 2, wherein a concentration of an n-type impurity in the n-type impurity region of the first semiconductor film of the memory cell is equal to a concentration of an n-type impurity of an n-type impurity region formed in the second semiconductor film of the n-channel thin film transistor.

4. The memory device according to claim 2, wherein a concentration of a p-type impurity in the p-type impurity region of the first semiconductor film of the memory cell is equal to a concentration of a p-type impurity of a p-type impurity region formed in the third semiconductor film of the p-channel thin film transistor.

5. A semiconductor device comprising:

a memory cell array including a memory cell;

a circuit for writing data in the memory cell array and reading data from the memory cell array;

an antenna; and

a signal processing circuit, wherein the signal processing circuit processes a signal received with the antenna and supplies a signal to the antenna,

wherein the memory cell comprises;

a first semiconductor film including an n-type impurity region and a p-type impurity region that are adjacent to each other;

a first conductive film which is formed over the first semiconductor film and which is connected to the n-type impurity region;

a second conductive film which is formed over the first conductive film; and

an organic compound layer interposed between the first conductive film and the second conductive film; and

a third conductive film which is formed over the first semiconductor film and which is connected to the p-type impurity region,

wherein the signal processing circuit includes an n-channel thin film transistor, a p-channel thin film transistor, and a capacitor, and

wherein the first semiconductor film of the memory cell is formed over the same insulating surface as a second semiconductor film of the n-channel thin film transistor, a third semiconductor film of the p-channel thin film transistor, and a fourth semiconductor film of the capacitor.

6. The semiconductor device according to claim 5, wherein a concentration of an n-type impurity in the n-type impurity region of the first semiconductor film of the memory cell is equal to a concentration of an n-type impurity of an n-type impurity region formed in the second semiconductor film of the n-channel thin film transistor.

7. The semiconductor device according to claim 5, wherein a concentration of a p-type impurity in the p-type impurity region of the first semiconductor film of the memory cell is equal to a concentration of a p-type impurity of a p-type impurity region formed in the third semiconductor film of the p-channel thin film transistor.