Thin film transistor array panel and method for manufacturing the same

• US 7,858,982 B2
• Filed: 08/29/2005
• Issued: 12/28/2010
• Est. Priority Date: 09/24/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Je-Hun, Jeong, Chang-Oh, Kim, Joo-Han, Cho, Beom-Seok
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): Kim; Jay C
• Application Number:
  US11/215,067
• Publication Number:
  US 20060076562A1
• Time in Patent Office: 1,947 Days
• Field of Search: 257/59, 257/72, 257/223, 257/52, 257/57, 257/66, 257/E29.273, 257/E29.151, 349/141
• US Class Current: 257/59
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode

Abstract

The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Claims

1. A thin film transistor array panel comprising:

an insulating substrate;

a gate line formed on the insulating substrate and comprising a gate electrode;

a gate insulating layer formed on the gate line;

a semiconductor layer formed on the gate insulating layer and overlapping the gate electrode;

diffusion barriers formed on the semiconductor layer;

ohmic contact layers disposed between the semiconductor layer and the diffusion barriers;

a data line crossing the gate line and comprising a source electrode partially contacting the diffusion barriers;

a drain electrode partially contacting the diffusion barriers and facing the source electrode; and

a pixel electrode electrically connected to the drain electrode,

wherein the diffusion barriers comprise silicide including nitrogen, or silicon doped with an n-type impurity and including nitrogen.

2. The thin film transistor array panel of claim 1, wherein the diffusion barriers have a substantially same planar pattern as the ohmic contact layers.

3. The thin film transistor array panel of claim 1, wherein the ohmic contact layers comprise the same material as the diffusion barriers except nitrogen.

4. The thin film transistor array panel of claim 1, wherein the data line comprises first to third conductor layers, the first and third conductor layers comprising Mo or a Mo alloy, and the second conductor layer comprising Al or an Al alloy.

5. The thin film transistor array panel of claim 1, further comprising color filters formed between the pixel electrode and the data line, and the drain electrode.

6. The thin film transistor array panel of claim 5, further comprising a passivation layer formed between the pixel electrode and the color filters.

7. The thin film transistor array panel of claim 6, further comprising an interlayer insulating layer formed between the color filters and the data line, drain electrode, and semiconductor layer.

8. The thin film transistor array panel of claim 1, wherein the pixel electrode has a plurality of cutouts partitioning a pixel area into a plurality of domains.

9. The thin film transistor array panel of claim 1, wherein the diffusion barriers have a thickness between 10 Å

and 100 Å

.