Checkerboarded high-voltage vertical transistor layout

• US 7,859,037 B2
• Filed: 02/16/2007
• Issued: 12/28/2010
• Est. Priority Date: 02/16/2007
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Parthasarathy, Vijay, Manley, Martin H.
• Primary Examiner(s): Zarneke; David A
• Assistant Examiner(s): Anya; Igwe U
• Application Number:
  US11/707,418
• Publication Number:
  US 20080197397A1
• Time in Patent Office: 1,411 Days
• Field of Search: 257/302, 257/E29.262
• US Class Current: 257/302
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, a transistor fabricated on a semiconductor die is arranged into sections of elongated transistor segments. The sections are arranged in rows and columns substantially across the semiconductor die. Adjacent sections in a row or a column are oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Claims

1. A transistor comprising:

a semiconductor die;

a plurality of transistor segments organized into a plurality of sections, the sections being arranged substantially across the semiconductor die, each section being substantially square, each transistor segment having a racetrack shape with a length and a width, each transistor segment including;

a pillar that includes an extended drain region that extends in a vertical direction through the semiconductor die;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

wherein a first section comprises transistor segments arranged in a side-by-side relationship with the length oriented in a first lateral direction, and a second section comprises transistor segments arranged in the side-by-side relationship with the length oriented in a second lateral direction substantially orthogonal to the first direction, the first section being disposed adjacent the second section.

2. The transistor of claim 1 wherein the pillar further comprises a source region disposed near a top surface of the semiconductor die, and a body region that vertically separates the source region from the extended drain region.

3. The transistor of claim 1 further comprising a gate disposed within the first and second dielectric regions adjacent the body region, the gate being insulated from the body region and the first and second field plates.

4. The transistor of claim 1 wherein the length is at least 20 times greater than the width.

5. The transistor of claim 1 wherein a fourth section comprises transistor segments arranged in the side-by-side relationship with the length oriented in the first lateral direction, and a third section comprises transistor segments arranged in the side-by-side relationship with the length oriented in the second lateral direction, the first section being disposed adjacent the second section in the second lateral direction and adjacent the third section in the first lateral direction, the fourth section being disposed adjacent the second section in the first lateral direction and adjacent the third section in the second lateral direction.

6. The transistor of claim 1 wherein a ratio of the length to the width of the transistor segments in the first and second sections is in a range of about 30 to 80.

7. The transistor of claim 1 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.

8. A transistor comprising:

a semiconductor die;

a plurality of transistor segments organized into a plurality of sections, each transistor segment having a length and a width, the length being at least 20 times greater than the width, each transistor segment including;

a pillar of a semiconductor material, the pillar including an extended drain region that extends in a vertical direction through the die;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

the sections being arranged in rows and columns substantially across the semiconductor die, adjacent sections in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent sections extends in a first direction, and the length of the transistor segments in a second one of the adjacent sections extends in a second direction, the first direction being substantially orthogonal to the second direction.

9. The transistor of claim 8 wherein the pillar further comprises a source region disposed near a top surface of the semiconductor die, and a body region that vertically separates the source region from the extended drain region.

10. The transistor of claim 9 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.

11. The transistor of claim 8 wherein the pillar extends in the first and second lateral directions to form a racetrack-shaped ring or oval.

12. The transistor of claim 8 wherein a ratio of the length to the width of the transistor segments in the first and second sections is in a range of about 30 to 80.

13. The transistor of claim 8 wherein the plurality of sections comprise 2N sections, where N is an integer greater than or equal to one.

14. A semiconductor wafer comprising:

a substrate;

a plurality of die arranged on the substrate in rows and columns, each die including a transistor having a plurality of transistor segments, each transistor segment having a length that extends substantially across the die and a width, the transistor segments of each die being arranged in a side-by-side relationship along the width substantially across the die, each transistor segment including;

a pillar of a semiconductor material, the pillar including a source region disposed near a top surface of the die, and an extended drain region that extends in a vertical direction through the substrate, the pillar extending in the first and second lateral directions to form a racetrack-shaped ring or oval;

first and second dielectric regions disposed on opposite sides of the pillar, respectively, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar;

first and second field plates respectively disposed in the first and second dielectric regions, the first and second field plates being fully insulated from the extended drain region, the first field plate being laterally surrounded by the pillar, and the second field plate laterally surrounding the pillar;

adjacent die in a row or a column being oriented such that the length of the transistor segments in a first one of the adjacent die extends in a first direction and the length of the transistor segments in a second one of the adjacent die extends in a second direction, the first direction being substantially orthogonal to the second direction.

15. The semiconductor wafer of claim 14 wherein each transistor segment further comprises a body region that vertically separates the source and extended drain regions.

16. The semiconductor wafer of claim 15 further comprising a trench gate structure that includes first and second gate members respectively disposed in the first and second dielectric regions near a top of the pillar adjacent the body region.

17. The semiconductor wafer of claim 15 wherein a ratio of the length to the width of the transistor segments is in a range of about 50 to 150.

18. The semiconductor wafer of claim 15 wherein each of the plurality of die are substantially square.

19. The semiconductor wafer of claim 15 wherein each of the plurality of die are substantially identical.