Memory having a vertical access device

• US 7,859,050 B2
• Filed: 01/22/2007
• Issued: 12/28/2010
• Est. Priority Date: 01/22/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengiing, Werner
• Primary Examiner(s): Wilson; Allan R
• Application Number:
  US11/656,125
• Publication Number:
  US 20080173920A1
• Time in Patent Office: 1,436 Days
• Field of Search: 257/437, 257/E31.119, 257/E31.12, 257/E21.029, 257329-334, 438/72
• US Class Current: 257/331
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate

Abstract

Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.

Claims

1. A memory array for a memory device, comprising:

a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising;

a storage device; and

an access device formed in the substrate that is coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the array further comprising;

a plurality of recesses each formed in the semiconductor substrate that includes a pair of opposing side walls and a floor extending there between, the side walls including active regions of the access device having a selected conductivities, wherein the active regions are confined to the side walls;

a conductive film structure that includes non-contiguous portions partially disposed on opposing side walls of the recess;

a dielectric layer interposed between the active regions and the conductive film structure; and

a plurality of trenches formed between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposing side walls of the plurality of recesses, and having a depth greater than a depth of the recesses;

with

a plurality of other trenches formed between adjacent ones of the recesses, substantially in parallel with the recesses, and having a depth greater than a depth of the recesses.

2. The memory array of claim 1, wherein the recess extends into the substrate to a recess depth, and the conductive film structure extends along respective side walls of the recess to a depth that is less than the recess depth.

3. The memory array of claim 1, wherein the active regions extend into the side walls to a first depth, and the conductive film structure extends along respective side walls of the recess to a second depth that is greater than the first depth.

4. The memory array of claim 3, wherein the conductive film structure further comprises an upper edge, wherein the upper edge is recessed within the recess to a third depth that is less than the first depth and the second depth.

5. The memory array of claim 1, wherein the conductive film structure comprises a lower edge that extends away from an intersection of the side walls and the floor.

6. The memory array of claim 1, wherein the dielectric layer further comprises a trench dielectric layer that substantially covers the floor and the pair of opposing side walls.

7. The memory array of claim 1, wherein the active regions are doped to impart at least one of an n+ and a p−

conductivity to the active regions.

8. The memory array of claim 1, wherein the storage device further comprises a three-dimensional capacitor structure.

9. A memory array for a memory device, comprising:

a plurality of memory cells formed on a semiconductor substrate and coupled to word lines and generally perpendicular bit lines formed on the substrate, each memory cell further comprising;

a plurality of storage devices; and

a plurality of access devices formed in the substrate that are operably coupled to the storage device and to a selected one of the word lines and a selected one of the bit lines, the array further comprising;

a plurality of recesses each formed in the semiconductor substrate that extends between the access devices and includes a pair of opposing side walls and a floor extending there between, wherein the side walls include active regions of the access devices, wherein the active regions are confined solely to the side walls;

a conductive film structure that includes non-contiguous portions at least partially disposed on opposing side walls of the recess;

a dielectric layer interposed between the active regions and the conductive film structure; and

a plurality of trenches formed between adjacent ones of the recesses, extending in a direction substantially perpendicular to the pairs of opposing side walls of the plurality of recesses, and having a depth greater than a depth of the recesses;

with

a plurality of other trenches formed between adjacent ones of the recesses, substantially in parallel with the recesses, and having a depth greater than a depth of the recesses.

10. The memory array of claim 9, wherein the recess extends into the substrate to a recess depth, and the conductive film structure extends along respective side walls of the recess to a depth that is less than the recess depth.

11. The memory array of claim 9, wherein the active regions extend into the side walls to a first depth, and the conductive film structure extends along respective side walls of the recess to a second depth that is greater than the first depth.

12. The memory array of claim 11, wherein the conductive film structure further comprises an upper edge, wherein the upper edge is recessed within the recess to a third depth that is less than the first depth and the second depth.

13. The memory array of claim 9, wherein the conductive film structure comprises a lower edge that extends away from an intersection of the side walls and the floor.

14. The memory array of claim 9, wherein the dielectric layer further comprises a trench dielectric layer that substantially covers the floor and the pair of opposing side walls.

15. The memory array of claim 9, wherein the active regions are doped to impart at least one of an n+ and a p−

conductivity to the active regions.

16. The memory array of claim 9, wherein the storage device further comprises a three-dimensional capacitor structure.

17. The memory array of claim 9, further comprising a terminal portion that includes a first side and an opposing second side, wherein the terminal portion adjoins one of the opposing side walls, and is substantially aligned with the recess.

18. The memory array of claim 17, wherein the terminal portion is comprised of a dielectric material.

19. The memory array of claim 17, wherein the conductive film extends along the terminal portion.

20. The memory array of claim 19, further comprising an end portion of the terminal portion that extends between the first side and the opposing second side, wherein the conductive film continuously extends along the first side, the end portion and onto the opposing second side.

21. The memory array of claim 19, further comprising a contact structure coupled to the conductive film.