Independently accessed double-gate and tri-gate transistors in same process flow

• US 7,859,053 B2
• Filed: 01/18/2006
• Issued: 12/28/2010
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doyle, Brian S., Chang, Peter L. D.
• Primary Examiner(s): Richards; N Drew
• Assistant Examiner(s): Lee; Jae
• Application Number:
  US11/335,103
• Publication Number:
  US 20060128131A1
• Time in Patent Office: 1,805 Days
• Field of Search: 438/365, 438/366, 438/283, 438/157, 438/164, 257/207, 257/331, 257/365, 257/347
• US Class Current: 257/347
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET

Abstract

A method for fabricating double-gate and tri-gate transistors in the same process flow is described. In one embodiment, a sacrificial layer is formed over stacks that include semiconductor bodies and insulative members. The sacrificial layer is planarized prior to forming gate-defining members. After forming the gate-defining members, remaining insulative member portions are removed from above the semiconductor body of the tri-gate device but not the I-gate device. This facilitates the formation of metallization on three sides of the tri-gate device, and the formation of independent gates for the I-gate device.

Claims

1. An integrated circuit formed by a process that includes:

forming at least two semiconductor bodies, wherein the semiconductor bodies have overlying insulative members;

forming a sacrificial layer over the at least two semiconductor bodies and their overlying insulative members;

planarizing the sacrificial layer;

patterning the sacrificial layer to form a gate-defining member and removing portions of the insulative members to form remaining portions of the insulative members on the semiconductor bodies;

forming a dielectric material adjacent the gate-defining member;

covering the remaining portion of one of the insulative members;

removing the remaining portion of another one of the insulative members after covering the remaining portion of one of the insulative members;

removing the gate-defining member;

forming an insulative layer and gate electrode layer within a trench defined by removal of the gate-defining member; and

planarizing the gate electrode layer to form two gate electrodes separated by the remaining portion of one of the insulative members on one of the semiconductor bodies, and to form another gate electrode on another one of the semiconductor bodies.

2. The integrated circuit of claim 1, including planarizing the dielectric material to expose remaining portions of insulative members.

3. The integrated circuit of claim 2, wherein the semiconductor bodies comprise monocrystalline silicon.

4. The integrated circuit of claim 3, wherein the insulative members comprise silicon nitride.

5. The integrated circuit of claim 1, wherein the sacrificial layer comprises polysilicon.

6. The integrated circuit of claim 4, wherein planarizing comprises chemical-mechanical polishing.

7. The integrated circuit of claim 1, including forming a hardmask layer over the sacrificial layer after planarizing.

8. The integrated circuit of claim 7, wherein the hardmask layer includes at least one of a silicon oxynitride layer, a silicon nitride layer, and silicon-rich-silicon-nitride layer.

9. The integrated circuit of claim 1, wherein planarizing is further characterized as using an etch-back process to planarize the surface of the sacrificial layer.