Systems and methods for integrated circuits comprising multiple body biasing domains

• US 7,859,062 B1
• Filed: 09/30/2004
• Issued: 12/28/2010
• Est. Priority Date: 02/02/2004
• Status: Active Grant

• Current Assignee: Meta Platforms, Inc. (f/k/a Facebook, Inc.)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Koniaris, Kleanthes G., Burr, James B., Masleid, Robert Paul
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US10/956,722
• Time in Patent Office: 2,280 Days
• Field of Search: 257/371, 257/511, 324/158.1, 716/5
• US Class Current: 257/371
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.

Claims

1. A semiconductor device comprising:

an epitaxy layer including;

a border region of a first conductivity type, wherein the border region extends to a first depth and forms a continuous structure around a first region; and

a buried region of the first conductivity type connected to the border region to form a bottom for the first region, wherein the buried region is located internally with respect to the epitaxy layer, wherein the border region and the buried region are configured to electrically isolate a first body biasing voltage of the first region from a second body biasing voltage of a second region; and

a substrate of a second conductivity type, wherein the epitaxy layer of the second conductivity type is formed on the substrate.

2. The semiconductor device of claim 1 further comprising:

a metal layer on a surface of the border region.

3. The semiconductor device of claim 1, wherein the buried region is planar, and wherein the epitaxy layer further includes:

a second border region of the second conductivity type, wherein the second border region extends to a second depth and forms a second continuous structure around the first region, wherein the border region forms the continuous structure around the first region and the second border region.

4. The semiconductor device of claim 3 further comprising:

a metal layer on a surface of the second border region.

5. The semiconductor device of claim 1 further comprising:

a first transistor of the first conductivity type partially located in the first region and partially located in the border region.

6. The semiconductor device of claim 5 further comprising:

a first contact connected to the first region to receive the first body biasing voltage for the first transistor.

7. The semiconductor device of claim 1 further comprising:

a first transistor of the second conductivity type located in the border region.

8. The semiconductor device of claim 7 further comprising:

a first contact connected to the border region to receive the first body biasing voltage for the first transistor.

9. A semiconductor device comprising:

an epitaxy layer including;

a first transistor of a first conductivity type;

a second transistor of a second conductivity type;

a border region of the first conductivity type, wherein the border region extends to a first depth and forms a continuous structure around a first region including the first and second transistors; and

a buried region of the first conductivity type connected to the border region to form a bottom for the first region, wherein the buried region is located internally with respect to the epitaxy layer, wherein the border region and the buried region are configured to electrically isolate a first body biasing voltage of the first region from a second body biasing voltage of a second region; and

a substrate of the second conductivity type, wherein the epitaxy layer of the second conductivity type is formed on the substrate.

10. The semiconductor device of claim 9 further comprising:

a metal layer on a surface of the border region.

11. The semiconductor device of claim 9, wherein the buried region is planar, and wherein the epitaxy layer further includes:

a second border region of the second conductivity type, wherein the second border region extends to a second depth and forms a second continuous structure around the first region including the first and second transistors, wherein the border region forms the continuous structure around the first region and the second border region.

12. The semiconductor device of claim 11 further comprising:

a metal layer on a surface of the second border region.

13. The semiconductor device of claim 9 further comprising:

a first contact connected to the first region to receive the first body biasing voltage for the first transistor.

14. The semiconductor device of claim 13 further comprising:

a well of the first conductivity type located in the first region, wherein the well includes the second transistor.

15. The semiconductor device of claim 14 further comprising:

a second contact connected to the well to receive a third body biasing voltage for the second transistor.

16. The semiconductor device of claim 14, wherein the well is connected to the buried region to receive a third body biasing voltage for the second transistor.

17. A semiconductor device comprising:

an epitaxy layer including;

a first border region of a first conductivity type, wherein the first border region extends to a first depth and forms a first continuous structure around a first region;

a first buried region of the first conductivity type connected to the first border region to form a bottom for the first region, wherein the first buried region is located internally with respect to the epitaxy layer;

a second border region of the first conductivity type, wherein the second border region extends to a second depth and forms a second continuous structure around a second region; and

a second buried region of the first conductivity type connected to the second border region to form a bottom for the second region, wherein the second buried region is located internally with respect to the epitaxy layer,

wherein the first border region and the first buried region are configured to electrically isolate a first body biasing voltage of the first region from a second body biasing voltage of the second region, and

wherein the second border region and the second buried region are configured to electrically isolate the second body biasing voltage of the second region from the first body biasing voltage of the first region; and

a substrate of a second conductivity type, wherein the epitaxy layer of the second conductivity type is formed on the substrate.

18. The semiconductor device of claim 17 further comprising:

a first metal layer on a surface of the first border region; and

a second metal layer on a surface of the second border region.

19. The semiconductor device of claim 17, wherein the first and second buried regions are planar, and wherein the epitaxy layer further includes:

a third border region of the second conductivity type, wherein the third border region extends to a third depth and forms a third continuous structure around the first region, wherein the first border region forms the first continuous structure around the first region and the third border region.

20. The semiconductor device of claim 19 further comprising:

a metal layer on a surface of the third border region.

21. The semiconductor device of claim 17, wherein the first region includes a first plurality of transistors of the first conductivity type and a second plurality of transistors of the second conductivity type.

22. The semiconductor device of claim 21 further comprising:

a first contact connected to the first region to receive the first body biasing voltage for the first plurality of transistors.

23. The semiconductor device of claim 22 further comprising:

a well of the first conductivity type located in the first region, wherein the well includes the second plurality of transistors; and

a second contact connected to the well to receive a third body biasing voltage for the second plurality of transistors.