Semiconductor device and method of forming embedded passive circuit elements interconnected to through hole vias

• US 7,859,085 B2
• Filed: 11/30/2009
• Issued: 12/28/2010
• Est. Priority Date: 05/27/2008
• Status: Active Grant

• Current Assignee: Stats Chippac Limited
• Original Assignee: Stats Chippac Limited
• Inventors: Do, Byung Tai, Pagaila, Reza A., Lin, Yaojian
• Primary Examiner(s): Lee; Calvin
• Application Number:
  US12/627,884
• Publication Number:
  US 20100072570A1
• Time in Patent Office: 393 Days
• Field of Search: 438/113, 438/629, 438/667, 438/675, 257/621, 257/698, 257E23141-E23179
• US Class Current: 257/621
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 : using a laser
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor die has a first insulating material disposed around a periphery of the die. A portion of the first insulating material is removed to form a through hole via (THV). Conductive material is deposited in the THV. A second insulating layer is formed over an active surface of the die. A first passive circuit element is formed over the second insulating layer. A first passive via is formed over the THV. The first passive via is electrically connected to the conductive material in the THV. The first passive circuit element is electrically connected to the first passive via. A third insulating layer is formed over the first passive circuit element. A second passive circuit element is formed over the third insulating layer. A fourth insulating layer is formed over the second passive circuit element. A plurality of semiconductor die is stacked and electrically interconnected by the conductive via.

Claims

1. A semiconductor device, comprising:

a semiconductor die;

a first insulating layer formed around the semiconductor die;

a conductive through hole via (THV) formed in the first insulating layer;

a conductive layer formed over the semiconductor die and first insulating layer to electrically connect the conductive THV to a contact pad on the semiconductor die;

a second insulating layer formed over an active surface of the semiconductor die; and

a first passive circuit element formed over the second insulating layer.

2. The semiconductor device of claim 1, further including a plurality of stacked semiconductor die electrically interconnected through the conductive THV.

3. The semiconductor device of claim 1, further including a discrete device disposed adjacent to semiconductor die and electrically connected to the conductive THV.

4. A semiconductor device, comprising:

a semiconductor die;

a first insulating layer formed around the semiconductor die;

a conductive through hole via (THV) formed in the first insulating layer;

a second insulating layer formed over an active surface of the semiconductor die;

a first passive circuit element formed over the second insulating layer; and

a first conductive layer formed on the conductive THV, the first passive circuit element being electrically connected to the conductive THV through the first conductive layer.

5. The semiconductor device of claim 4, further including:

a third insulating layer formed over the first passive circuit element;

a second passive circuit element formed over the third insulating layer; and

a fourth insulating layer formed over the second passive circuit element.

6. The semiconductor device of claim 5, further including a second conductive layer formed on the first conductive layer, the second passive circuit element being electrically connected to the first conductive layer through the second conductive layer.

7. A semiconductor device, comprising:

a semiconductor die having a peripheral region;

a first insulating material deposited in the peripheral region of the semiconductor die;

a conductive through hole via (THV) formed in the first insulating material;

a conductive layer formed over the semiconductor die and first insulating material to electrically connect the conductive THV to a contact pad on the semiconductor die;

a first insulating layer formed over an active surface of the semiconductor die;

a first passive circuit element formed over the first insulating layer; and

a first passive via formed on the conductive THV, the first passive circuit element being electrically connected to the conductive THV through the first passive via.

8. The semiconductor device of claim 7, further including:

a second insulating layer formed over the first passive circuit element;

a second passive circuit element formed over the second insulating layer; and

a third insulating layer formed over the second passive circuit element.

9. The semiconductor device of claim 8, further including a second passive via formed on the first passive via, the second passive circuit element being electrically connected to the first passive via through the second passive via.

10. The semiconductor device of claim 7, wherein the peripheral region is singulated through the conductive THV to form a conductive half via.

11. The semiconductor device of claim 7, wherein the peripheral region is singulated through the first insulating material to form a conductive full via.

12. The semiconductor device of claim 7, further including a plurality of stacked semiconductor die electrically interconnected through the conductive THV.

13. The semiconductor device of claim 7, further including a discrete device disposed adjacent to semiconductor die and electrically connected to the conductive THV.

14. A semiconductor device, comprising:

a semiconductor die;

a first insulating layer formed around the semiconductor die;

a conductive through hole via (THV) formed in the first insulating layer;

a second insulating layer formed over an active surface of the semiconductor die;

a first passive circuit element formed over the second insulating layer; and

a first conductive layer formed over the conductive THV, the first passive circuit element being electrically connected to the conductive THV through the first conductive layer.

15. The semiconductor device of claim 14, further including a second conductive layer formed over the semiconductor die and first insulating layer to electrically connect the conductive THV to a contact pad on the semiconductor die.

16. The semiconductor device of claim 14, further including:

a third insulating layer formed over the first passive circuit element;

a second passive circuit element formed over the third insulating layer; and

a fourth insulating layer formed over the second passive circuit element.

17. The semiconductor device of claim 16, further including a second conductive layer formed over the first conductive layer, the second passive circuit element being electrically connected to the first conductive layer through the second conductive layer.

18. The semiconductor device of claim 14, further including a plurality of stacked semiconductor die electrically interconnected through the conductive THV and first conductive layer.

19. A semiconductor device, comprising:

a semiconductor die;

a first insulating layer formed around the semiconductor die;

a conductive through hole via (THV) formed in the first insulating layer;

a first passive circuit element formed over the active surface of the semiconductor die; and

a first conductive layer formed over the conductive THV, the first passive circuit element being electrically connected to the conductive THV through the first conductive layer.

20. The semiconductor device of claim 19, further including a second conductive layer formed over the active surface of the semiconductor die and first insulating layer to electrically connect the conductive THV to a contact pad on the semiconductor die.

21. The semiconductor device of claim 19, further including:

a second insulating layer formed over the first passive circuit element;

a second passive circuit element formed over the second insulating layer; and

a third insulating layer formed over the second passive circuit element.

22. The semiconductor device of claim 21, further including a second conductive layer formed over the first conductive layer, the second passive circuit element being electrically connected to the first conductive layer through the second conductive layer.

23. The semiconductor device of claim 19, further including a plurality of stacked semiconductor die electrically interconnected through the conductive THV.

24. The semiconductor device of claim 19, further including a discrete device disposed adjacent to semiconductor die and electrically connected to the conductive THV.