Pad area and method of fabricating the same

• US 7,859,604 B2
• Filed: 10/02/2006
• Issued: 12/28/2010
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kang, Tae-Wook, Kwak, Won-Kyu, Jeong, Chang-Yong
• Primary Examiner(s): Andújar; Leonardo
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/540,543
• Publication Number:
  US 20070076393A1
• Time in Patent Office: 1,548 Days
• Field of Search: 361/767, 349/42, 349/43, 349/139, 349/149, 349/151, 349/152
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13452 Conductors connecting driver circuitry and terminals of panels
• CPC Class Codes: G02F 1/13456 Cell terminals located on one side of the display only
• CPC Class Codes: H05K 1/111 Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/0373 Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
• CPC Class Codes: H05K 3/323 by applying an anisotropic conductive adhesive layer over an array of pads
• CPC Class Codes: H05K 3/361 Assembling flexible printed circuits with other printed circuits
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A pad area and a method of fabricating the same, wherein the pad area is formed on a substrate to contact a chip on glass (COG) or a chip on flexible printed circuit (COF) with the substrate. Changing a lower structure of the pad area increases contact points between conductive balls and an interconnection layer or reduces a step difference between an interconnection layer and a passivation layer to enhance and ensure electrical connection.

Claims

1. A pad area, comprising:

a substrate;

an embossed layer having an embossed pattern disposed on the substrate;

an interconnection layer disposed on the embossed layer and covering at least the embossed pattern of the embossed layer, the interconnection layer covering at least an entire upper surface of the embossed layer, and the interconnection layer being a portion of at least one of source and drain electrodes and a gate electrode; and

a passivation layer covering an edge of the interconnection layer.

2. The pad area as claimed in claim 1, further comprising a conductive ball disposed on the interconnection layer.

3. The pad area as claimed in claim 1, further comprising a gate electrode pattern disposed between the substrate and the embossed layer.

4. The pad area as claimed in claim 1, further comprising at least one of a first electrode pattern, a second electrode pattern, and a reflective layer pattern disposed on the interconnection layer.

5. The pad area as claimed in claim 1, wherein the embossed layer is formed of a single embossed pattern.

6. The pad area as claimed in claim 1, wherein the embossed layer is formed of at least two embossed patterns.

7. The pad area as claimed in claim 1, wherein the embossed layer is portions of an interlayer insulating layer and a gate insulating layer.

8. The pad area as claimed in claim 1, wherein the embossed layer is formed of at least one of a silicon layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer.

9. The pad area as claimed in claim 1, wherein the interconnection layer is flat when the embossed layer thereunder is formed of a single embossed pattern.

10. The pad area as claimed in claim 1, wherein the interconnection layer is uneven when the embossed layer thereunder is formed of at least two embossed patterns.

11. The pad area as claimed in claim 1, wherein the interconnection layer is higher than the passivation layer.

12. The pad area as claimed in claim 1, wherein the passivation layer is a portion of a planarization layer or a pixel defining layer.

18. The pad area as claimed in claim 1, wherein the conductive ball is directly on the interconnection layer.

19. The pad area as claimed in claim 1, wherein the passivation layer is completely separated from the embossed layer by the interconnection layer.

13. A method of fabricating a pad area, comprising:

forming a substrate;

forming a gate insulating layer and an interlayer insulating layer on the substrate, and patterning the layers to form an embossed layer;

depositing source and drain electrode materials on the substrate having the embossed layer, and then patterning the electrode materials to form an interconnection layer covering at least the embossed layer; and

forming a passivation layer covering an edge of the interconnection layer.

14. The method as claimed in claim 13, further comprising, before forming the gate insulating layer,

depositing a gate electrode material on the substrate, and then patterning the gate electrode material to form a gate electrode pattern.

15. The method as claimed in claim 13, further comprising, after forming the passivation layer,

forming an auxiliary interconnection layer on the interconnection layer and the passivation layer.

16. A method of fabricating a pad area, comprising:

preparing a substrate;

forming a semiconductor layer pattern on the substrate;

forming a gate insulating layer on the substrate having the semiconductor layer pattern;

forming a gate electrode pattern on the gate insulating layer;

forming an embossed pattern having a width larger than the gate electrode pattern on the substrate having the gate electrode pattern;

forming source and drain electrode materials on the substrate having the embossed pattern, and then patterning the electrode materials to form an interconnection layer covering at least the embossed pattern; and

forming a passivation layer covering an edge of the interconnection layer.

17. The method as claimed in claim 16, further comprising, after forming the passivation layer,

forming an auxiliary interconnection layer on the interconnection layer and the passivation layer.