Liquid crystal display device and fabricating method thereof using three mask process

• US 7,859,639 B2
• Filed: 12/20/2005
• Issued: 12/28/2010
• Est. Priority Date: 12/24/2004
• Status: Expired due to Fees

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Ahn, Byung Chul
• Primary Examiner(s): Healy; Brian M.
• Assistant Examiner(s): INADOMI, MICHAEL J
• Application Number:
  US11/311,553
• Publication Number:
  US 20060139548A1
• Time in Patent Office: 1,834 Days
• Field of Search: 349/147, 349/148, 349/141, 349188-192, 349/187, 438/30
• US Class Current: 349/187
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/13629 Multilayer wirings

Abstract

A LCD device includes a gate line on a substrate and a data line crossing the gate line to define a pixel area; a thin film transistor source and drain electrodes; a common line parallel to the gate line; a common electrode extended from the common line and a pixel electrode extending from the drain electrode wherein the gate line and the common line have a first conductive layer group having at least double conductive layers, and the common electrode is formed by an extension of at least one transparent conductive layer of the common line; and the gate line, the source electrode and the drain electrode have a second conductive layer group having at least double conductive layers, and the pixel electrode is formed by an extension of at least one transparent conductive layer of the drain electrode.

Claims

1. A method of fabricating a liquid crystal display device, comprising:

a first mask process of forming a first mask pattern group including a gate line, a gate electrode connected to the gate line and a common line substantially parallel to the gate line having a first conductive layer group structure including at least double conductive layers which have a lowermost layer of transparent conductive layer and upper conductive layer of metal layer, and a common electrode extended from the lowermost layer of transparent conductive layer of the common line on a substrate;

a second mask process of forming a gate insulating film on the first mask pattern group and a semiconductor pattern on the gate insulating film; and

a third mask process of forming a third mask pattern group including a data line, a source electrode connected to the data line and a drain electrode opposite the source electrode having a second conductive layer group structure including at least double conductive layers which have a lowermost layer of transparent conductive layer and upper conductive layer of metal layer, and a pixel electrode extended from the lowermost layer of transparent conductive layer of the drain electrode, wherein the data line, the source electrode and the drain electrode are over the gate insulating film and the source electrode and the drain electrode are on both ends of the semiconductor pattern.

2. The method as claimed in claim 1, further comprising forming a storage capacitor by an overlap of the drain electrode with a portion of the common electrode and the gate insulating film therebetween.

3. The method as claimed in claim 1, wherein the upper conductive layer of metal layer of the first and second conductive layer groups has at least one of a single layer structure and a double layer structure of Mo, Ti, Cu, AlNd, Al, Cr, a Mo-alloy, a Cu-alloy or an Al-alloy.

4. The method as claimed in claim 1, wherein the first mask process includes forming a data link formed of the first conductive layer group to have a portion overlapped with the data line, and the second mask process includes forming a contact hole passing through the gate insulating film to connect the data link with the data line.

5. The method as claimed in claim 4, wherein the first mask process includes:

forming the first conductive layer group on the substrate;

forming first photo-resist patterns having different thicknesses by photolithography using one of a half tone mask and a diffractive exposure mask;

forming the first mask pattern group including the common electrode having the first conductive layer group structure by an etching process using the first photo-resist patterns; and

etching the common electrode so that only the lowermost layer of the first conductive layer group remains as the common electrode by the etching process using the first photo-resist patterns.

6. The method as claimed in claim 5, wherein the first mask process further includes forming a lower pad electrode connected to at least one of the gate line, the data line and the common line from the first conductive layer,

the second mask process includes forming a contact hole passing through the gate insulating film to expose the lower pad electrode, and

the third mask process includes forming an upper pad electrode to be connected, via said contact hole, to the lower pad electrode from the lowermost layer of the second conductive layer group.

7. The method as claimed in claim 6, wherein the upper pad electrode is formed of the same layer as the lowermost layer of the data line.

8. The method as claimed in claim 6, wherein the second mask process includes:

forming a gate insulating film, an amorphous silicon layer and an amorphous silicon layer doped with an impurity on the first mask pattern group;

forming second photo-resist patterns of a different thickness by photolithography using one of a half tone mask and a diffractive exposure mask; and

forming contact holes and the semiconductor pattern by an etching process using the second photo-resist pattern.

9. The method as claimed in claim 8, wherein the third mask process includes:

forming the second conductive layer group on the gate insulating film with the semiconductor pattern;

forming third photo-resist patterns of a different thickness using one of a half tone mask and a diffractive exposure mask;

patterning the second conductive layer group by an etching process using the third photo-resist pattern to provide a third mask pattern group including the upper pad electrode;

removing the amorphous silicon layer doped with an impurity exposed between the source electrode and the drain electrode; and

etching the pixel electrode and the upper pad electrode to remain lowermost layers thereof by an etching process using the third photo-resist pattern as a mask.

10. The method as claimed in claim 5, wherein the first mask process further includes forming a pad connected to at least one of the gate line, the data line and the common line from the first conductive layer, and

the second mask process further includes forming a contact hole exposing the pad.

11. The method as claimed in claim 10, wherein forming the pad includes:

forming the pad having a lower pad electrode and an upper pad electrode of the first conductive layer group structure by the etching process using the photo-resist patterns; and

exposing the lower pad electrode passing through the upper pad electrode to expose the lower pad electrode by the etching process using an ashed photo-resist pattern.

12. The method as claimed in claim 11, wherein the contact hole is not overlapped with the upper pad electrode so that the etching process exposes the lower pad electrode.

13. The method as claimed in claim 4, wherein the contact hole is provided at an area to be sealed by a sealant upon joining of the substrates.

14. The method as claimed in claim 4, further comprising forming an alignment film on the data line, the source electrode, the drain electrode, the pixel electrode and the contact hole.

15. The method as claimed in claim 1, wherein the data line, the source electrode, the drain electrode and said pixel electrode are provided at an area to be sealed by a sealant upon joining of the substrates.

16. The method as claimed in claim 1, further comprising forming an alignment film on the data line, the source electrode, the drain electrode and the pixel electrode.

17. The method as claimed in claim 1, wherein the semiconductor pattern is formed at a position provided with a thin film transistor.

18. The method as claimed in claim 1, wherein at least one of the first and second conductive groups has step coverage having a substantially rectangular stepwise shape.

19. The method as claimed in claim 1, wherein at least two layers of the semiconductor pattern, the source electrode, the drain electrode and the pixel electrode have step coverage having a substantially rectangular stepwise shape.